LECTURE:15-17 MEMORY

INTERFACING IN 8085
COURSE INSTRUCTOR: DR. DEVYANI GUPTA
 Recall…
• uP does not have any memory, it needs to be interfaced
• External memory support in 8085:
• Address bus size = 16 bits
• Max. number of address = 216 = 64kb
• Every location can store 1 byte
• Max. memory that can be interfaced with 8085 = 64KB
• We can interface a memory chip with max size 64KB or
several memory chips with combined size not exceeding
64KB
MEMORY
1. Primary Memory:
Also called main memory, it is directly accessible by the CPU. It includes:
•RAM (Random Access Memory):
• Volatile memory, meaning data is lost when the power is turned off.
• Used to store data that the CPU needs to access quickly for ongoing tasks.
• Types:
• SRAM (Static RAM): Faster and more expensive; used for cache memory.
• DRAM (Dynamic RAM): Slower and less expensive; used for system memory.
•ROM (Read-Only Memory):
• Non-volatile memory that holds data permanently, even when the power is off.
• Contains critical boot-up programs (firmware) for the system.
• Types:
• PROM (Programmable ROM): Can be programmed once.
• EPROM (Erasable Programmable ROM): Can be erased using UV light and
reprogrammed.
• EEPROM (Electrically Erasable Programmable ROM): Can be erased and
reprogrammed electronically, making it more flexible.
2. Secondary Memory:
Also known as auxiliary memory or storage, it is used to store data and programs long-term. It is slower
than primary memory but can store much larger amounts of data.
MEMORY ICs
SIZE EPROM RAM
1KB 2708 6108
2KB 2716 6116
4KB 2732 6132
8KB 2764 6164
16KB 27128 61128
32KB 27256 61256
FUNCTIONAL PIN DIAGRAM OF MEMORY CHIPS
What is the starting address of this chip?
MULTIPLE MEMORY ADDRESS RANGE
ADDRESS DECODING TECHNIQUES
• PARTIALLY DECODED ADDRESSING
• some address lines are in ‘don’t care’ state for CHIP SELECT
• FULLY DECODED ADDRESSING
• All address lines are used for CHIP SELECT
Q: If the starting address is 0351 H. Find the ending address of 1KB
memory when interfaced with 8085 uP.

Total number of address Lines for 210 𝑚𝑒𝑚𝑜𝑟𝑦 = 10

If the starting address = 0000 H

Then, the ending address = 03FF H

If starting address = 0351 H

Then, ending address = 0351 H + 03FF H = 0750 H
Q: If the ending address is BABF H. Find the starting address of 4KB
memory when interfaced with 8085 uP.

Total number of address Lines for 22 × 210 𝑚𝑒𝑚𝑜𝑟𝑦 = 12

If the starting address = 0000 H

Then, the ending address = 0FFF H

If ending address = BABF H

Then, ending address = BABF H – 0FFF H = AAC0 H
Q: Draw an interfacing of a 4K EPROM having starting address 2000H with
8085 uP. Use demultiplexed address/data lines and 3-to-8 decoder (74LS138)
For memory interfacing, 4 types of signals are required:
1. Address Lines
2. Data Lines Address Lines = 4K = 22 × 210 = 212 = 12 lines
Data Lines = 8 Lines
3. Control Lines Control Signals = RD*
4. Chip Select Chip Select = remaining address lines

Memory Mapping

Memory Chip 𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0 Memory Address

4K EPROM 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000 H

0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 2FFF H
 𝐴11 − 𝐴0 𝐷7 − 𝐷0 𝑦1−
𝐴15 − 𝐴8

ALE G
Latch 𝐴7 − 𝐴0 Add. Data OE*
𝐴𝐷7 − 𝐴𝐷0 74LS373

OC* EPROM 4K

8085 uP
𝐷7 − 𝐷0 CS*

IO/M* C 𝑦0−
RD* B 𝑦1− MEMR*
WR* A 𝑦2− MEMW*
𝑦3−
74138 𝑦4−
3:8 𝑦5− IOR*
decoder 𝐴15 𝐴14 𝐴13 𝐴12
𝑦6− IOW*
𝑦7−
Q: Interfacing 4K EPROM and 16K RAM with 8085 uP. Write the address range
for both the memory chips and also the address decoding logic.
For memory interfacing, 4 types of signals are required:
1. Address Lines
2. Data Lines
3. Control Lines
4. Chip Select

4K EPROM 16K RAM

Address Lines = 4K = 22 × 210 = 212 = 12 lines Address Lines = 16K = 24 × 210 = 214 = 14 lines
Data Lines = 8 Lines Data Lines = 8 Lines
Control Signals = RD* Control Signals = RD*, WR*
Chip Select = remaining address lines Chip Select = remaining address lines
 Memory Mapping

Memory Chip 𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0 Memory Address

4K EPROM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 H

0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFF H

16K RAM 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000 H

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFF H
 𝐴11 − 𝐴0

𝐷7 − 𝐷0

𝐴13 − 𝐴0

𝐷7 − 𝐷0

𝑦1−

𝑦2−
𝑦1−
𝐴15 − 𝐴8

G Add. Data OE* Add. Data OE* WR*

ALE
Latch 𝐴7 − 𝐴0
𝐴𝐷7 − 𝐴𝐷0 74LS373
EPROM 4K 16K RAM
OC* CS* CS*
8085 uP
𝐷7 − 𝐷0

IO/M* C 𝑦0−
RD* B 𝑦1− MEMR*
WR* A 𝑦2− MEMW* 𝐴15 𝐴14 𝐴13 𝐴12 𝐴15 . 𝐴14
𝑦3−
74138 𝑦4−
3:8 𝑦5− IOR*
decoder
𝑦6− IOW*
𝑦7−
Q: Interface 8K EPROM and 16K RAM with 8085 uP using chips of 4K EPROM
and 8K RAM. Show decoding of IC with 74LS138 Decoder.

4K EPROM 8K RAM

Address Lines = 4K = 22 × 210 = 212 = 12 lines Address Lines = 8K = 23 × 210 = 213 = 13 lines
Data Lines = 8 Lines Data Lines = 8 Lines
Control Signals = RD* Control Signals = RD*, WR*
Chip Select = remaining address lines Chip Select = remaining address lines
 Memory Mapping

Memory Chip 𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0 Memory Address

4K EPROM-1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 H

0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFF H

4K EPROM-2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1000 H

0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFF H

8K RAM-1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000 H

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFF H

8K RAM-2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000 H

0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5FFF H
 𝐴12 − 𝐴0
𝐴11 − 𝐴0

𝐷7 − 𝐷0

𝐷7 − 𝐷0
𝑦1−

𝑦1−

𝑦2−
𝐴15 − 𝐴8
Add. Data OE* Add. Data OE* WR*
ALE G 𝐴7 − 𝐴0
Latch 4K EPROM -1 8K RAM-1
𝐴𝐷7 − 𝐴𝐷0 74LS373
CS* CS*
OC*

𝐴15 𝐴14 𝐴13 𝐴12

𝐴15 𝐴14 𝐴13

8085 uP
𝐷7 − 𝐷0

𝐴12 − 𝐴0
𝐴11 − 𝐴0

𝐷7 − 𝐷0

𝐷7 − 𝐷0
𝑦1−

𝑦1−

𝑦2−
IO/M* C 𝑦0−
RD* B 𝑦1− MEMR* Add. Data OE* Add. Data OE* WR*
WR* A 𝑦2− MEMW*
4K EPROM -2 8K RAM-1
𝑦3−
𝑦4− CS* CS*
74138
𝑦5−

𝐴15 𝐴14 𝐴13

3:8 IOR*

𝐴15 𝐴14 𝐴13 𝐴12

decoder
𝑦6− IOW*
𝑦7−
MEMORY ICs (with 8-bit Data)
SIZE EPROM RAM
1KB 2708 6108
2KB 2716 6116
4KB 2732 6132
8KB 2764 6164
16KB 27128 61128
32KB 27256 61256
 Q: Interface 8X4 bits memory with 8085 uP.

Data size = 4 bits

Number of address =8
Number of address lines required = 3 (from 23 ) 𝐴3

WR* CS* RD*

𝐴2
𝐴1
8X4 memory
𝐴0
OBSERVATIONS
• This is an example of partially decoded
addressing
• Only 4 data lines has been connected
𝐷3 𝐷2 𝐷1 𝐷0
 Q: Interface two 4X4 bits memory with 8085 uP such that the two memories
form the lower and upper nibble of data of 8085.
Data size = 4 bits
Number of address per memory =4
Number of address lines required = 3 (from 22 )
𝐴2
𝐴2

OBSERVATIONS WR* CS* RD*

WR* CS* RD*
• This is an example 𝐴1 𝐴1
of partially 4X4 memory 4X4 memory
decoded 𝐴0 𝐴0
addressing

𝐷7 𝐷6 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0
 PRACTICE QUESTIONS

Q1: Interface 12KB RAM with 8085 uP using IC 6232. Use IO/M* in CS* logic
generation
Q2: Interface 1KB RAM with 8085 uP using 1K X 4 RAM (IC 2114/2142).

Q3: Interface 4KB RAM with 8085 uP using 1K X 4 ICs. Allot addresses starting
from 4000H, 4800H, C400H and CC00H. Use IO/M* in CS* generation

Q4: Interface 2KB EPROM and 2KB RAM with 8085 uP such that there is 2K gap
in between addresses.