Memory and Memory Interfacing
Ajay Singh Raghuvanshi
Memory
Memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 8,16, 24, 32, 64 or as many as 128 bits. Memory Can be classified into two categories
RAM
ROM
Types of RAM memory
Static Random Access Memory (SRAM)
Doesnt need refreshing ,Retains contents as long as power applied to the chip
Access time around 10 nanoseconds, Can be Used for cache memory Dynamic Random Access Memory (DRAM)
Contents are constantly refreshed 1000 times per second
Access time 60 70 nanoseconds Synchronous Dynamic Random Access Memory (SDRAM)
Quicker than DRAM
Access time less than 60 nanoseconds Direct Rambus Dynamic Random Access Memory (DRDRAM)
New type of RAM architecture
Access time 20 times faster than DRAM, More expensive Cache memory
Small amount of memory typically 256 or 512 kilobytes
Temporary store for often used instructions Faster for CPU to access than main memory Level 1 cache is built within the CPU (internal) Level 2 cache may be on chip or nearby (external)
Types of ROM
Programmable
Empty
Read Only Memory (PROM)
of data when manufactured
May
be permanently programmed by the user
Erasable Programmable Read Only Memory (EPROM)
Can
be programmed, erased and reprogrammed
The EPROM chip has a small window on top allowing it to be erased by shining ultra-violet light on it reprogramming the window is covered to prevent new contents being erased time is around 45 90 nanoseconds
After
Access
Types of ROM
Electrically
Erasable Programmable Read Only Memory
electrically without using ultraviolet light
(EEPROM)
Reprogrammed
Must
be removed from the computer and placed in a special machine to do this times between 45 and 200 nanoseconds
Access
Flash
ROM
to EEPROM can be reprogrammed while still in the computer
Similar
However, Easier Used
to upgrade programs stored in Flash ROM time is around 45 90 nanoseconds
to store programs in devices e.g. modems
Access
Typical RAM chip
Chip select 1 Chip select 2 Read Write 7-bit address CS1 CS2 RD WR AD 7
128 x 8 RAM
8-bit data bus
CS1 CS2 0 0 0 1 1 0 1 0 1 0 1 1
RD x x 0 0 1 x
WR x x 0 1 x x
Memory function Inhibit Inhibit Inhibit Write Read
State of data bus High-impedence High-impedence High-impedence Input data to RAM Output data from RAM
Typical ROM chip
Chip select 1 Chip select 2 CS1 CS2 512 x 8 ROM 9-bit address AD 9 8-bit data bus
Memory Interfacing
MEMORY ADDRESS MAP
Address space assignment to each memory chip on a me Example:
Component RAM RAM RAM RAM ROM 1 2 3 4 Hexa address 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF 0200 - 03FF Address bus
10 9
0 0 0 0 1 0 0 1 1 x
8 7 6 5
0 1 0 1 x x x x x x x x x x x x x x x x
4 3 2 1
x x x x x x x x x x x x x x x x x x x x
The 74LS138, 3-to-8 line decoder
Example: Design a 64K-8 EPROM interface for the 8086 microprocessor using EPROM chips (8K x 8). The ROM memory starts at address F0000HFFFFFH.
Assignment 2
Design memory interface to be used with MPU 8086 in Minimum mode with following specifications
ROM
: 128 K: using 8 ROM chips of same size RAM : 256 K: using 8 RAM chips of same size Draw the memory map of the system showing the chip address range for each chip
Memory Map For problem
A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A9 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range F0000 F0FFF F1000 F1FFF F2000 F2FFF F3000 F3FFF F4000 F4FFF F5000 F5FFF F6000 F6FFF F7000 F7FFF F8000 F8FFF F9000 F9FFF FA000 FAFFF FB000 FBFFF FC000 FCFFF FD000 FDFFF FE000 FEFFF FF000 FFFFF
Chip No ROM1
ROM2
ROM3
ROM4
ROM5
ROM6
ROM7
ROM8
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
RAM7
RAM8
