EEE201 CMOS Digital Integrated Circuits

CMOS IC Layout Design Project

Student

Course

Professor

Institution

Date
This report presents the design of an IC layout for a 2-input CMOS NOR gate. The emphasis on
coming up with a compact and optimized dimension of the transistor. In order to compute the
aspect ratios of each of the transistors, CMOS primary parameters such as carrier mobility,
threshold voltage and oxide capacitance are accounted for. However, PMOS has lower hole
mobility than electrons in NMOS. Due to this, the aspect ratio of PMOS has been advanced to
maintain the required balance. The layout compactness has been achieved by arranging
transistors efficiently and routing inputs and outputs carefully , considering critical factors like
minimum feature size and alignment errors to enhance manufacturability .

In order to implement the logic operation of the NOR gate, two PMOS transistors have been
arranged in series to perform the pull-up functionality, where they ensure that the output F is at
the logic 1 high voltage while two NMOS transistors have been configure in parallel
arrangement to perform the pull-down operation where they ensure that the output F is at logic 0
low voltage.

INTRODUCTION

The objective of this report is to design and present a good IC layout of a 2-input NOR gate for
CMOS. The number of masks and the area of layout utilized in the process of fabrication have
been minimized to ensure accurate functionality of the network. Feature size, gate oxide
capacitance, threshold voltage and carrier mobility are some of the key factors that have been
considered based on their relevance with CMOS technology. These parameters guide in sizing
PMOS and NMOS transistors to ensure proper current drive is maintained and ensure operation
balance. Computations on the transistor aspect ratios and the use of the metal-1 layers as well as
the polysilicon are part of the design process initially elaborated. A graphical layout of the IC
showing how the outputs and inputs ae arranged, adherence to constraints as well as the
transistor arrangements are also included. Therefore, in order to come up with a compact NOR
gate circuit which is manufacturable, this work has ensured that CMOS design principles have
been appropriately applied.

CIRCUIT DESIGN AT SCHEMATIC LEVEL

The voltage levels, drive current, switching sped of this device is directly proportional to its size
determination. Both NMOS and PMOS circuit networks must work together to implement the
NOR logic successfully. It has been taken into account the fact that only one path is required to
remain active at a time. The Pull Up Network which is the PMOS transistors. They connected in
series network and are responsible for pulling up the output F to a higher voltage which is simply
at logic 1. The Pull-Down Network which is the NMOS transistors. They are connected in
parallel network and are responsible for pulling down the output F to a lower voltage at logic 0.
rise and fall time balance, power dissipation verses reliability, speed verses power consumption,
noise margin and speed are the trade-off performance considered in the design.

Below is the truth table of the circuit network.

As shown in the aspect ratio section below, the NMOS and PMOS sizes have been computed as
an equivalent respective aspect ratios. The minimum fabrication technology allowed is the
channel length. Its width is adjusted in order to achieve the desired current balance and carrier
mobility.
Pseudo-NMOS NOR gate can is an alternative circuit to implement 2-input CMOS NOR gate.
This circuit significantly reduces the number of transistors used.

In order to implement this design, its pull-down network has each of the NMOS transistor gates
connected to one of the two inputs. Their drain terminal is connected to the output while the
source terminal is connected to the ground, and the two NMOS transistors are connected in
parallel.

Its pull-up network has got a single PMOS transistor which is the one that actually acts as the
pull-up device. The PMOS gate is connected to the ground terminal which maintains it at on
condition. Its power supply is connected to the PMOS source terminal.

The common node is the point where the output is taken because this is where the PMOS
transistor’s drain terminal connects to the NMOS transistors.

The merits of Pseudo-NMOS NOR gate as an alternative to a 2-input CMOS NOR gate include
faster pull-down, its design is simple its transistor count is significantly reduced. However, it has
the following disadvantages; Its noise margin is poor, its unsuitable for low-power applications,
it has a degraded high output voltage, and a static power dissipation.

IC LAYOUT DESIGN

The below CMOS parameters were provided I order to come up with the desired design.
Optimal aspect ratio and the shared diffusion regions to reduce the number of diffusion contacts
are the specific optimizations considered in order to minimize the area of chip while increasing
its performance.

The layout design considerations considered to reduce the parasitic capacitance, inductance and
resistance are shared diffusion, shorter interconnections and guard rings.

Aspect Ratio

Aspect ratio is the ratio of the width of the transistor to its length. In order to ensure a symmetric
behavior between PMOS and NMOS transistors, the aspect ratio of the PMOS should be
increased to compensate for its lower µp even though they differ in mobility, (µn>µp), both of
them should ensure equal drive strengths (ID).
The design rules taken into consideration are as follows: well substrate contact rule, spacing and
overlap rules and minimum feature size.

The trade-off performance considerations are interconnected parasitic, routing simplicity and
manufacturability.

IC layout

Below are changes made in order to come up with the layout:

Transistor sizing adjustments, where by in the schematic, transistor sizes are based on theoretical
performance but in layout drawing, adjustments are made to meet routing constraints and
physical area.

Routing optimization for PMOS, where by the schematic suggested equal sizes for NMOS and
PMOS while in the layout, PMOS are usually increased in width to account for their lower
mobility. This change in turn ensure performance goals are met like voltage levels and speed are
met.
 SUMMARY AND CONCLUSION

In order to accommodate both the pull-down and pull-up network circuits using proper
configuration of the NMOS and PMOS, the layout was optimized painstakingly and this
significantly helped in realizing the NOR gate logic. As long as the transistor functionality are
observed in strict nature, constraints of the minimum layout area and proper routing taken into
consideration, the principles of designing CMOS can bear good fruits in the practical work, as
proven by this nice design and implementation of the CMOS 2-input NOR gate IC layout. The
reliability and versatility of CMOS in integrated network design has been illustrated by this
project through the efficient use of CMOS technology in implementing logic functions for the
digital circuits.

It is usually very important to ensure a balance exist between manufacturing constraints and
design objectives, and this is an additional achievement that this design has actually achieved.
Embedding metal-1 layers for interconnections and poly-silicon layers for gate connections has
made the layout compact and manufacturable. In order to prevent interference while optimizing
the area, the output F, the inputs A and B, have all been routed together. These are the major
factors that will ensure the design is scalable for enhanced applications, and suitable for to be
integrated into larger circuits systems
Bibliography
[1]
H. H. Radamson et al., “State of the Art and Future Perspectives in Advanced CMOS
Technology,” Nanomaterials, vol. 10, no. 8, p. 1555, Aug. 2020, doi:
https://doi.org/10.3390/nano10081555. [2] B. Davari, “CMOS technology: Present
and future,” Jan. 2003, doi: https://doi.org/10.1109/vlsic.1999.797216. [3] A.
Chatzigeorgiou, S. Nikolaidis, and I.
Tsoukalas, “A modeling technique for CMOS gates,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 18, no. 5, pp. 557–575, May 1999, doi:
https://doi.org/10.1109/43.759070.
[4]
C. S. Bamji et al., “A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image
Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC,” IEEE
Journal of Solid-State Circuits, vol. 50, no. 1, pp. 303–319, Jan. 2015, doi:
https://doi.org/10.1109/jssc.2014.2364270.
[5]
J. F. Bulzacchelli et al., “A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm
SOI CMOS Technology,” vol. 47, no. 12, pp. 3232–3248, Dec. 2012, doi:
https://doi.org/10.1109/jssc.2012.2216414.