3rd Mediterranean Conference on Embedded Computing MECO - 2014 (ECyPS’2014) Budva, Montenegro

An Energy-Aware Dynamic Scheduling

Algorithm for Hard Real-Time Systems

Christina K. Houben and Wolfgang A. Halang

Chair of Computer Engineering
Fernuniversität in Hagen
Hagen, Germany
[email protected]

Abstract—Based on the Earliest Deadline First policy guaran- objects fed by accumulators or batteries. But conventional
teeing timeliness for hard real-time systems, we propose an processors or programmable logic controllers as widely used in
enhanced EDF algorithm that varies distinct processor modes embedded hard real-time systems can benefit from energy-
with time. Processor modes are determined by supply voltage, aware scheduling as well.
frequency and performance requirements, allowing for discrete
control of the processors’ energy consumption. Thus, processors II. RELATED WORK
using the enhanced policy will dissipate less energy and, at the
same time, adhere to the deadlines of hard real-time systems.
In the literature, algorithms for energy-aware scheduling
are distinguished by various criteria. As with conventional
Keywords–Minimisation of energy consumption; Dynamic scheduling strategies, there are scheduling policies for single
voltage-frequency scaling; Earliest Deadline First scheduling; and for multiprocessor systems. Furthermore, the related work
Hard real-time systems is based on distinct policies, some of them guarantee
timeliness, while most of them do not. Finally, one can divide
I. INTRODUCTION the algorithms into static and dynamic ones. The EDF
algorithm from [1] is dynamic, timely and made for single
The Earlierst Deadline First (EDF) policy presented in [1]
processor systems.
is a timely scheduling algorithm used for computing processes
(tasks) in hard real-time systems. Such processes have to be The first methods to lower the energy consumption of
completely executed before certain deadlines expire, the processors were based on distinct shutdown modes and a single
damages resulting otherwise would be intolerable. For working mode. In a shutdown mode with lower energy
instance, avionics systems are subject to such real-time dissipation it then takes more time to awake the processor than
conditions, as we shall see in later sections. in other shutdown modes. For this purpose, [2, 3] introduce
several strategies.
We shall use the EDF policy as foundation and enhance it
to become energy-aware. EDF is a dynamic scheduling For automation technology, the concept of graceful
strategy and works as follows. The processes ready for degradation is very important. It means, that a less accurate, but
execution are sorted by their deadlines forming a queue. The with fewer instructions calculated result of a computing
process with the earliest deadline is executed first. If one or process may still be useful. A straightforward example for this
more further processes arrive during execution of the ready is to prematurely terminate an iterative approximation. Then,
task set, they are properly inserted into the queue. If the the result is less precise, but for hard real-time systems it is
deadline of a newly arriving process is earlier than the one of better to have an imprecise result at the right time than an exact
the task currently being executed, the latter is pre-empted and one after the due date. The option of fewer instructions to
the new process executed instead. This policy guarantees that decrease the energy consumption of systems is exploited in [4].
all processes are executed before their deadlines expire, if this
is possible by any scheduling strategy at all. Other scheduling methods make use of additional
assumptions, e.g. on the percentage of communication with
Now, we want to enhance this scheduling strategy in such a peripheral devices. Data transfers cannot be accelerated with
way that it calculates not only which process to execute next, faster processors. Scheduling strategies taking this fact into
but also the performance with which the processor should ope- consideration are proposed in [5]. For programmable logic
rate next. Lower performance saves energy, but it also decrea- controllers, the use of process images for input and output
ses processing speed. Thus, the enhanced algorithm has to take prevents such communication overhead.
measures in order to guarantee that all deadlines will be met.
Embedded systems also need facilities for synchronisation.
Lower processor performance prolongs the lifetime of A scheduling algorithm that takes critical sections into account
electronic devices such as smartphones or lightweight flying is proposed in [6].

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 3rd Mediterranean Conference on Embedded Computing MECO - 2014 (ECyPS’2014) Budva, Montenegro

III. MOTIVATIONAL EXAMPLES

Foremost, we look at a simple example. We consider a
single process that takes 4800 processor cycles to be executed.
It should be scheduled on a processor with two modes. The
faster mode has a frequency of Fmax = 600 MHz and a power
consumption of Pmax = 4.2 W. The slower mode has a
frequency of Fmin = 300 MHz and requires Pmin = 1.3 W.
Hence, the process takes 8 μs in the faster mode with an energy
consumption of 33.6 μJ, and in the slower mode, although it
takes 16 μs, it consumes only 20.8 μJ of energy. This fact is
illustrated in Fig. 1.
Figure 1. Comparison of execution time and
The first microprocessor with voltage hopping produced in energy consumption in a faster and a slower mode.
large quantities was the Transmeta Crusoe. It offers five
distinct modes, see Table I with values of [7]. From [8] one can
grasp the data of the Intel Pentium M which provides six TABLE I. TRANSMETA CRUSOE PROCESSOR
modes. The processor of AMD described in [9] even runs in 28
modes. For the same voltage it can operate at many different Voltage Frequency Performance
frequencies. A newer example is a chip by IBM [10] achieving 1.600 V 667 MHz 5.3 W
30% energy savings by reducing its frequency from 3.86 GHz
to 1.75 GHz. 1.500 V 600 MHz 4.2 W
1.350 V 533 MHz 3.0 W
Now we have a look on task sets of hard real-time systems
and, in particular, of avionics systems. Such task sets usually 1.225 V 400 MHz 1.9 W
contain 5 to 200 different members, which can be subdivided 1.200 V 300 MHz 1.3 W
into periodic and aperiodic tasks. The latter tasks are only
scheduled on demand. Periodic tasks are characterised by
activation frequencies or periods. In avionics, task runtimes are TABLE II. AIR TRAFFIC CONTROL SYSTEM
not only approximated, but specified exactly as these systems
are usually highly safety-critical. Table II shows the task set of Function Frequency Runtime Response t.
an air traffic control system [11]. Other typical task sets are the Report Correlation 15 μs 100 μs
one of an avionic system with 24 processes [12], and the armed
flight system with 31 processes [13]. A bigger task set with 177 Cockpit Display 750 Hz 120 μs 200 μs
members is mentioned in [14]. Unfortunately, the authors do Controller Display 7500 Hz 12 μs 300 μs
not provide its characteristics. Aperiodic Requests 250 μs 360 μs
IV. ENERGY MODEL Voice Advisory 600 Hz 75 μs 780 μs
A processor’s energy consumption is composed of the Terrain Avoidance 40 μs 2930 μs
contributions by its single components, which can be driven Conflict Detection 60 μs 3970 μs
with individual voltages and frequencies. A component’s Final Approach 100 Hz 33 μs 6810 μs
energy consumption consists of a static and a dynamic part.
The static part is caused by leakage, is also present when the
processor is in a non-operating state, and grows with the chip’s
temperature rising due to operation. Scheduling algorithms
minimising this static part, in particular the thermal energy When a chip’s supply voltage is decreased, the frequency
dissipation, are considered in [15]. The dynamic part has to be lowered, too. A simple model [18] uses V ~ F. During
dominates, however, when a processor is operating. The voltage scaling, transient frequency oscillations occur, whose
performance P of a CMOS processor depends on the duration is estimated as 6 ms/V in [19]. In principle, a
aggregated capacitance C of its transistors, the voltage V and processor can operate during such oscillations, although in [7,
the frequency F as follows [16]: 8] a period is specified during which processors may be unable
to work. The models of the previous paragraph imply the
P § ½CV²F. following lemma [20]:
The capacitance depends on the number of transistors. It Lemma 1. In a given mode, a processor’s energy consumption
can, thus, only be influenced during chip design. The other is minimised if and only if a process being executed terminates
physical quantities V and F of the chip can be changed during exactly at its deadline.
runtime by Dynamic Voltage-Frequency Scaling (DVFS). The
hardware implementation of DVFS is realised by voltage The reason is that P ~ V²F grows faster than the time delay
hopping [17]. due to frequency scaling.

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 3rd Mediterranean Conference on Embedded Computing MECO - 2014 (ECyPS’2014) Budva, Montenegro

V. EXISTENCE AND COMPUTABILITY OF A SOLUTION In the course of program executions on the processor, some
Let the task set 7 be composed of n periodic tasks Ti = (pi, tasks in 5 finish and others enter a state of being partially
ri, ai), where pi is the ith task’s period, ri its runtime in the executed. The finished tasks are removed from 5 and inserted
fastest processor mode and ai its response time. If a process is into 6, since the periodic ones will be scheduled again after
scheduled sporadically, i.e. on demand only, pi is set to the their period pi, and the other tasks could be re-scheduled on
minimum time span after which the task can be re-scheduled. demand at any time after expiration of their minimum waiting
Alternatively, the period can be replaced by the task’s durations pi. The shadow task set 6 contains all tasks which are
activation frequency. The runtimes must be real ones, i.e. not not ready, but are waiting to be activated. We have to keep
just approximations. They also contain the delays caused by the them into account because, in the worst case, all of them could
context switch(es) required to schedule the processes. In case become ready at the current point in time as results of
no response time is given for a certain process, its period will asynchronous events or temporal conditions.
be used. A processor’s discrete performance modes are given The set 7 is implemented in form of a list sorted in
by 0 = {M1, …, Mm} with Mi = (Vi, Fi, Pi) and Vi the voltage, ascending order of its elements’ deadlines owing to the EDF
Fi the frequency and Pi the performance of the ith mode. The policy. The members of 7 belonging to the subset 5 are
modes are sorted by their frequencies in descending order. marked by a bit each. When Algorithm 1 is invoked at instant
Hence, M1 is the fastest mode with the highest performance. tnow, the deadline of each shadow task i is set to tnow + ai.
Now, we formulate the energy-aware scheduling problem Performing this operation for all shadow tasks has a runtime
as a linear program in order to state it more clearly. Therein, xij complexity of 2(n).
denotes the runtime required to execute task Ti in mode Mj. To In the initialisation phase, 5 is empty and 6 contains all
cover the entire runtime of a process, the constraints known tasks. When a task becomes ready to be executed for
the first time, or resumes to the ready state, Algorithm 1 is
¦ j =1 xij = 1
m
and x ij ≥ 0 invoked to determine the task to be scheduled and, under worst
case conditions, to calculate the processor mode most energy-
have to be fulfilled. The penalty function to be minimised is efficient for executing the entire task set 7

E = ¦i =1 ¦ j =1 ri ⋅ xij ⋅ Pj .
n m
ALGORITHM 1: EDF POLICY WITH DVFS

Hence, the timeliness constraint [1] results in Initialisation:

5 = Ø; // 5 is the list of all ready tasks sorted with
a i ≥ ¦k =1 ¦ j =1 rk ⋅ x kj ⋅ F j ,
i m
// respect to their deadlines in ascending order.
6 = 7; // 6contains all shadow tasks that are currently
yielding the following linear program with nm variables as well // not scheduled.
as 2n constraints and non-negativity constraints:
When a task T[i] (re-) enters the ready state:
¦i =1 ¦ j =1 ri ⋅ xij ⋅ Pj :
n m
min{ E = Calculate deadlines of all tasks in 6; // ĺ 2(n)
a i ≥ ¦ k =1 ¦ j =1 rk ⋅ x kj ⋅ F j ,
i m
∀i = 1...n Sort 7 in ascending order of its elements’
deadlines and, at the same time,
¦ j =1 xij = 1 ,
m
∀j = 1...m Find in 7 the task T[j] with minimal slack; // ĺ 2(n log n)
x ij ≥ 0 } Move T[i] from 6 to 5; // ĺ 2(1)

A unique solution of it exists and can be computed with Accumulate the runtimes of tasks
T[1], …, T[j]; // ĺ 2(n)
runtime complexity 2(n²m²) by the Ellipsoid method [21]
under the assumption that the points in time when all tasks will Calculate the ideal frequency such that
be scheduled are known before. In the next section we go one the slack of T[j] vanishes; // ĺ 2(1)
step further and propose an algorithm even able to handle the Assign to T[1] the ideal frequency, or
scheduling problem in a dynamic setting, i.e. that it is not a first the next lower and then the next
priori known at which instants the tasks will be scheduled. higher frequency if the ideal mode is
VI. DYNAMIC SCHEDULING ALGORITHM not available. // ĺ 2(1)
In this section we develop an algorithm which decreases the In the next step, we have to find in 7 the task with minimal
energy consumption while, at the same time, all hard real-time slack. If we spread the runtime of all tasks starting at the first
conditions are met, that is, all tasks will properly finish before task in 7 until the one with the minimum slack in such a way
their respective deadlines expire. Therefore, we subdivide the that the last task’s slack vanishes, then the energy consumption
set 7 into the set 5 of ready tasks and the set 6of “shadow is minimised according to Lemma 1. We call this subset of 7
tasks”. The former contains all tasks already being scheduled. task group. During the search for the minimum slack we can, at

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 3rd Mediterranean Conference on Embedded Computing MECO - 2014 (ECyPS’2014) Budva, Montenegro

the same time, determine with complexity 2(n) the runtime of [3] S. Khuller, J. Li, and B. Saha, “Energy Efficient Scheduling via Partial
the task group in the fastest processor mode, from which the Shutdown”, Proc. of the 21st Annual ACM-SIAM Symposium on
Discrete Algorithms (SODA), 2010, pp. 1360−1372.
stretching frequency can be derived with complexity 2(1).
[4] H.-S. Yun, and J. Kim, “Reward-based Voltage Scheduling for
The resulting ideal frequency may not be available, since a Dynamic-priority Hard Real-time Systems”, Design Automation for
microprocessor using Vdd hopping has only a finite discrete set Embedded Systems 11, 2007, pp. 25−48.
of modes. If this is the case, then the next modes to be assigned [5] E. Bini, G. Buttazzo, and G. Lipari, “Speed Modulation in Energy-aware
are the two with neighbouring frequencies, namely the fre- Real-time Systems”, Proc. of the 17th Euromicro Conference on Real-
Time Systems (ECRTS), 2005, pp. 3−10.
quencies next lower and next higher to the ideal one. At least,
one of these modes is assigned to the task to be executed next. [6] R. Jejurikar, and R. K. Gupta, “Energy Aware EDF Scheduling with
Task Synchronization for Embedded Real Time Systems”, International
The overall runtime complexity of this novel energy-aware Workshop on Compilers and Operating Systems for Low Power, 2002,
pp. 71−76
EDF variant is 2(n log n) when a task turns ready and arrives
for execution. The only reason for this complexity not to be [7] M. Fleischmann, “Longrun Power Management”, White Paper, 2001.
just 2(n) is the sorting required by the underlying EDF. [8] Intel, “Enhanced Intel SpeedStep Technology for the Intel Pentium M
Processor”, White Paper, 2004.
VII. IMPLEMENTATION [9] AMD, “AMD PowerNow Technology Dynamically Manages Power and
Performance”, White Paper, 2000.
For the implementation of Algorithm 1 we selected the
high-level programming language PEARL90 [22], since it [10] M. Broyles, C. Francois, A. Geissler, G. Grout, M. Hollinger, T.
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an existing real-time operating system kernel mainly written in [11] W. Meilander, J. Baker, and M. Jin, “Predictable Real-time Scheduling
this language. Owing to the language’s high expressive power, for Air Traffic Control”, 2002.
the pseudocode instructions given above translate to only a few [12] J. A. Bannister, and K. S. Trivedi, “Task Allocation in Fault-tolerant
PEARL90 statements each in a straightforward way. First Distributed Systems”, Acta Informatica 20, 1983, pp. 261−281.
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processor modes confirm the theoretically raised expectations. Avionics Software Specification”, Technical Report, 1990.
[14] F. Eisenbrand, K. Kesavan, R. S. Mattikalli, M. Niemeier, A. W.
VIII. CONCLUSION AND FUTURE WORK Nordsieck, M. Skutella, J. Verschae, and A. Wiese, „Solving an
We started out from the conventional scheduling strategy, Avionics Real-time Scheduling Problem by Advanced IP-Methods”,
18th Annual European Symposium on Algorithms (ESA 2010), 2010,
that sorts all tasks by their deadlines and executes them in this pp. 11−22.
order with a fixed processor frequency and performance. The
[15] H. Huang, M. Fan, and G. Quan, “Thermal Aware Overall Energy
advantage of this policy is to guarantee timeliness in hard real- Minimization Scheduling for Hard Real-time Systems”, Sustainable
time systems. We proposed a new algorithm based on the EDF Computing 3 (4), 2013, pp. 274−285.
policy. It decreases the energy consumption and, at the same [16] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, „Low-power
time, observes all deadlines set. CMOS Digital Design”, IEEE Journal of Solid-State Circuits 27 (4),
1992, pp. 473−484.
For the future, we plan to evaluate our approach more
[17] C. Albea, C. Canudas de Wit, and F. Gordillo, “Control and Stability
thoroughly with simulations on task sets of avionic systems. Analysis for the Vdd-hopping Mechanism”, Control Applications &
Furthermore, we shall examine extensions of our algorithm that Intelligent Control (CCA & ISIC), 2009, pp. 320−325.
take critical sections into account and allow for shortening task [18] M. Weiser, B. Welch, A. Demers, and S. Shenker, „Scheduling for
runtimes in cases of overload by imprecise computations. Reduced CPU Energy”, Proc. of the 1st USENIX Conference on
Operating Systems Design and Implementation (OSDI), 1994.
ACKNOWLEDGMENTS [19] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava,
The authors thank Sebastian Houben for useful discussions “Power Optimization of Variable-voltage Core-based Systems”, Proc. of
that helped to enhance the quality of this paper. Further thanks the 35th Annual Design Automation Conference (DAC), 1998, pp.
176−181.
go to Dr. Panchalee Sukjit for help with the section Related
Work, and for the valuable comments of the reviewers. [20] T. Ishihara, and H. Yasuura, “Voltage Scheduling Problem for
Dynamically Variable Voltage Processors”, Proc. of the International
Symposium on Low Power Electronics and Design (ISLPED), 1998, pp.
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