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Assignment 1-1

This document is an assignment for the EEE413L/CSE413L/ETE419L course at North South University, requiring students to design and simulate a 2-bit comparator and a simple logic gates circuit using ModelSim, Xilinx, and Cadence. Students must provide screenshots of various stages of their design and synthesis processes and submit both a PDF and a hard copy of their work. The assignment emphasizes the importance of directory organization and documentation of the simulation and synthesis results.

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raheeb nazmul
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6 views12 pages

Assignment 1-1

This document is an assignment for the EEE413L/CSE413L/ETE419L course at North South University, requiring students to design and simulate a 2-bit comparator and a simple logic gates circuit using ModelSim, Xilinx, and Cadence. Students must provide screenshots of various stages of their design and synthesis processes and submit both a PDF and a hard copy of their work. The assignment emphasizes the importance of directory organization and documentation of the simulation and synthesis results.

Uploaded by

raheeb nazmul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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NORTH SOUTH UNIVERSITY

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING


EEE413L/CSE413L/ETE419L: Verilog HDL: Modeling, Simulation & Synthesis
ASSIGNMENT – 1

Instruction
 Write your name, ID, and section.

 Two designing problems are given. Simulate and synthesis both problems using ModelSim, Xilinx and
Cadence.

 Attach screenshots for each problem.

 Save the file in pdf format.

 Print and submit the hardcopy of your assignment. [Online submission is strictly prohibited]

Name: Mujahidul Islam ID: 2131765043 Section: 01

Problem 1
Design a 2-bit comparator using conditional operation of data flow modeling. Here A and B are 1-bit inputs. G,
E and L are 1-bit outputs. Truth table of 2-bit Comparator is given below. You need to test your design and
synthesis your design.

Attach screenshots of the following parts.


1. Main module.

2. Testbench.

3. Transcript after compiling using ModelSim.


4.Waveforms after complete simulation using ModelSim.

5.Using VNC viewer, make a directory in the form ‘Name_Section_Simulation’ [eg. Oshin_1_Simulation],
save the main module and testbench in that directory, and take a screenshot of that directory.
6.Waveform after complete simulation using Cadence.
7.RTL Schematic after synthesis using Xilinx.

8.Using VNC viewer, make a directory in the form ‘Name_Section_Synthesis’ [eg. Oshin_1_Synthesis], make
the four directories [constraints, lib, rtl, synthesis] inside that directory, save the main module inside rtl and take
screenshots changing directory to
I. rtl
II. Synthesis
[Note:Take screenshots after copying necessary files from root for synthesis]

9.Schematic after synthesis using Cadence.


Problem 2
A simple logic gates circuit is given below where x0, x1, x2, x3 are 1-bit inputs and g, f, h are
1-bit outputs. Simulate and synthesis your design.

Attach screenshots of the following parts.


1. Main module.
2.Testbench.

3.Transcript after compiling using ModelSim.

4.Waveforms after complete simulation using ModelSim.


5.Using VNC viewer, make a directory in the form ‘Name_Section_Simulation’ [eg. Oshin_1_Simulation],
save the main module and testbench in that directory, and take a screenshot of that directory.

6.Waveform after complete simulation using Cadence.


7.RTL Schematic after synthesis using Xilinx.

8.Using VNC viewer, make a directory in the form ‘Name_Section_Synthesis’ [eg. Oshin_1_Synthesis], make
the four directories [constraints, lib, rtl, synthesis] inside that directory, save the main module inside rtl and
screenshots changing directory to

I. rtl

II. Synthesis

[Note:Take screenshots after copying necessary files from root for synthesis]
9.Schematic after synthesis using Cadence.

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