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VHDL Assignment

The document outlines an assignment with four questions focused on VHDL design. It includes tasks such as deriving output expressions for a full subtractor, designing a logic circuit for a 3-bit binary number range, creating a warning system for water tanks, and implementing a two-bit adder with a 7-segment display. Each question requires simulation and the creation of specific waveform files for verification.

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Hnd Final
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18 views2 pages

VHDL Assignment

The document outlines an assignment with four questions focused on VHDL design. It includes tasks such as deriving output expressions for a full subtractor, designing a logic circuit for a 3-bit binary number range, creating a warning system for water tanks, and implementing a two-bit adder with a 7-segment display. Each question requires simulation and the creation of specific waveform files for verification.

Uploaded by

Hnd Final
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 01

INSTRUCTIONS:
1. Begin each question in a new project. Once completed, save your design as a zip file.
You will be given an email address to send the file.
2. Use VHDL design entry method for all the questions

Fig. 1.1: Full subtractor circuit diagram

QUESTION 1:
Derive the output expressions for the digital circuit shown in Fig. 1.1. Using Quartus II,
implement the design according to these expressions. Create a waveform file named
subtractor_circuit.vwf to simulate your design.

QUESTION 2:

Design a logic circuit that detects when a 3-bit binary number falls within the range of 2
(010) to 6 (110), inclusive. Use the VHDL selected signal assignment method to implement
the design. Simulate your circuit by creating a waveform file named logic_circuit.vwf, and
ensure it tests all possible input values from 000 to 111.

QUESTION 3:

A water reclamation plant needs to have a warning system to monitor its three water
overflow holding tanks. Each tank has a HIGH/LOW level sensor. Design a system that
activates a warning alarm whenever two or more tank levels are HIGH. Simulate your
design to verify its correctness. Ensure that the simulation confirms that the logic behaves as
expected across all input conditions.
QUESTION 4:
Design a two-bit adder in VHDL that adds two numbers (𝐴1 𝐴0 and 𝐵1 𝐵0) and produces a
three-bit output labeled 𝑋2 𝑋1 𝑋0, where 𝑋0 is the least significant bit and 𝑋2 represents
the carry bit. Display the result on a 7-segment display. Hint: Use the common cathode
configuration for the 7-segment display, as detailed in Table 1.1. Create a waveform file
named adder_circuit.vwf to simulate your design.
Table 1.1

s/n Pin Number Description

1 Pin 1 e-segment

2 Pin 2 d-segment

3 Pin 3 common

4 Pin 4 c-segment

5 Pin 5 Dot

6 Pin 6 b-segment

7 Pin 7 a-segment

8 Pin 8 common

9 Pin 9 f-segmenr

Fig. 1.2: 7-Segment Display 10 Pin 10 g-segment

Table 1.2: 7-segment common cathode type display truth table

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