SN74AVC8T245

SCES517K – DECEMBER 2003 – REVISED NOVEMBER 2023

SN74AVC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage

Translation and 3-State Outputs

1 Features The SN74AVC8T245 is compatible with a single-

supply system and can be replaced later with a '245
• Latch-up performance exceeds 100 mA per JESD
function, with minimal printed circuit board redesign.
78, Class II
• ESD protection exceeds JESD 22: This device is fully specified for partial-power-down
– 8000-V Human-Body Model (A114-A) applications using Ioff. The Ioff circuitry disables the
– 200-V Machine Model (A115-A) outputs, thus preventing damaging current backflow
– 1000-V Charged-Device Model (C101) through the device when it is powered down.
• Control inputs VIH/VIL levels are referenced to The VCC isolation feature allows both ports to be in
VCCA voltage the high-impedance state when either VCC input is at
• VCC isolation feature – if either VCC input is at GND.
GND, all I/O ports are in the high-impedance state
• Ioff supports partial power-down mode operation To put the device into the high-impedance state during
• Fully configurable dual-rail design allows each power up or power down, tie OE to VCC through a
port to operate over the full 1.4-V to 3.6-V power- pullup resistor; the current-sinking capability of the
supply range driver determines the minimum value of the resistor.
• I/Os are 4.6-V tolerant Package Information
• Maximum data rates:
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
– 170Mbps (VCCA < 1.8 V or VCCB < 1.8 V)
RHL (VQFN, 24) 5.5 mm × 3.5 mm
– 320Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
SN74AVC8T245 PW (TSSOP, 24) 7.8 mm × 6.4 mm
2 Applications DGV (TVSOP, 24) 5 mm × 6.4 mm
• Personal electronic (1) For more information, see Section 10.
• Industrial (2) The package size (length × width) is a nominal value and
• Enterprise includes pins, where applicable.
• Telecom
2
3 Description DIR
This 8-bit noninverting bus transceiver uses two
22
separate configurable power-supply rails. The OE
SN74AVC8T245 is optimized to operate with VCCA/
VCCB set at 1.4 V to 3.6 V. The device is operational 3
A1
with VCCA and VCCB as low as 1.2 V. The A port
is designed to track VCCA. VCCA accepts any supply
21
voltage from 1.2 V to 3.6 V. The B port is designed B1
to track VCCB. VCCB accepts any supply voltage from
1.2 V to 3.6 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V, 1.5-
V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. To Seven Other Channels

The SN74AVC8T245 is designed for asynchronous Logic Diagram (Positive Logic)

communication between data buses. The device
transmits data from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The output-enable
(OE) input can be used to disable the outputs so the
buses are effectively isolated.
The SN74AVC8T245 is designed so that the control
pins (DIR and OE) are supplied by VCCA.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.1 Overview................................................................... 15
2 Applications..................................................................... 1 6.2 Functional Block Diagram......................................... 15
3 Description.......................................................................1 6.3 Feature Description...................................................15
4 Pin Configuration and Functions...................................3 6.4 Device Functional Modes..........................................16
5 Specifications.................................................................. 4 7 Application and Implementation.................................. 17
5.1 Absolute Maximum Ratings........................................ 4 7.1 Application Information............................................. 17
5.2 ESD Ratings............................................................... 4 7.2 Typical Application.................................................... 17
5.3 Recommended Operating Conditions.........................5 7.3 Power Supply Recommendations.............................18
5.4 Thermal Information....................................................6 7.4 Layout....................................................................... 18
5.5 Electrical Characteristics.............................................6 8 Device and Documentation Support............................20
5.6 Switching Characteristics, VCCA = 1.2 V..................... 7 8.1 Documentation Support............................................ 20
5.7 Switching Characteristics, VCCA = 1.5 V ± 0.1 V.........7 8.2 Receiving Notification of Documentation Updates....20
5.8 Switching Characteristics, VCCA = 1.8 V ± 0.15 V.......8 8.3 Support Resources................................................... 20
5.9 Switching Characteristics, VCCA = 2.5 V ± 0.2 V.........9 8.4 Trademarks............................................................... 20
5.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V.....10 8.5 Electrostatic Discharge Caution................................20
5.11 Operating Characteristics........................................ 11 8.6 Glossary....................................................................20
5.12 Typical Total Static Power Consumption (ICCA + 9 Revision History............................................................ 20
ICCB).............................................................................11 10 Mechanical, Packaging, and Orderable
5.13 Typical Characteristics............................................ 12 Information.................................................................... 21
6 Detailed Description......................................................15

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4 Pin Configuration and Functions

VCCA

VCCB
VCCA 1 24 VCCB
DIR 2 23 VCCB
A1 3 22 OE 1 24
A2 4 21 B1 DIR 2 23 VCCB
A3 5 20 B2 A1 3 22 OE
A4 6 19 B3 A2 4 21 B1
A5 7 18 B4 A3 5 20 B2
A6 8 17 B5 A4 6 19 B3
A7 9 16 B6 A5 7 18 B4
A8 10 15 B7 A6 8 17 B5
GND 11 14 B8 A7 9 16 B6
GND 12 13 GND A8 10 15 B7
GND 11 14 B8
Figure 4-1. DGV or PW Package, 24-Pin TVSOP or 12 13
TSSOP (Top View)

GND

GND
Figure 4-2. RHL Package, 24-Pin VQFN (Top View)

Table 4-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
A1 3 I/O Input/output A1. Referenced to VCCA.
A2 4 I/O Input/output A2. Referenced to VCCA.
A3 5 I/O Input/output A3. Referenced to VCCA.
A4 6 I/O Input/output A4. Referenced to VCCA.
A5 7 I/O Input/output A5. Referenced to VCCA.
A6 8 I/O Input/output A6. Referenced to VCCA.
A7 9 I/O Input/output A7. Referenced to VCCA.
A8 10 I/O Input/output A8. Referenced to VCCA.
B1 21 I/O Input/output B1. Referenced to VCCB.
B2 20 I/O Input/output B2. Referenced to VCCB.
B3 19 I/O Input/output B3. Referenced to VCCB.
B4 18 I/O Input/output B4. Referenced to VCCB.
B5 17 I/O Input/output B5. Referenced to VCCB.
B6 16 I/O Input/output B6. Referenced to VCCB.
B7 15 I/O Input/output B7. Referenced to VCCB.
B8 14 I/O Input/output B8. Referenced to VCCB.
DIR 2 I Direction-control signal
GND 11, 12, 13 — Ground
3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced
OE 22 I
to VCCA.
VCCA 1 — A-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V
VCCB 23, 24 — B-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCCA,
Supply voltage –0.5 4.6 V
VCCB
I/O ports (A port) –0.5 4.6
VI Input voltage(2) I/O ports (B port) –0.5 4.6 V
Control inputs –0.5 4.6

Voltage range applied to any output A port –0.5 4.6

VO V
in the high-impedance or power-off state(2) B port –0.5 4.6
A port –0.5 VCCA + 0.5
VO Voltage range applied to any output in the high or low state(2) (3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current –50 50 mA
Continuous current through VCCA, VCCB, or GND –100 100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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5.3 Recommended Operating Conditions

See (1) (2) (3)
VCCI VCCO MIN MAX UNIT
VCCA Supply voltage 1.2 3.6 V
VCCB Supply voltage 1.2 3.6 V
1.2 V to 1.95 V VCCI × 0.65
High-level
VIH Data inputs 1.95 V to 2.7 V 1.6 V
input voltage
2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCI × 0.35
Low-level
VIL Data inputs 1.95 V to 2.7 V 0.7 V
input voltage
2.7 V to 3.6 V 0.8
1.2 V to 1.95 V VCCA × 0.65
High-level DIR
VIH 1.95 V to 2.7 V 1.6 V
input voltage (referenced to VCCA)
2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCA × 0.35
Low-level DIR
VIL 1.95 V to 2.7 V 0.7 V
input voltage (referenced to VCCA)
2.7 V to 3.6 V 0.8
VI Input voltage 0 3.6 V
Active state 0 VCCO
VO Output voltage V
3-state 0 3.6
1.2 V –3
1.4 V to 1.6 V –6
IOH High-level output current 1.65 V to 1.95 V –8 mA
2.3 V to 2.7 V –9
3 V to 3.6 V –12
1.2 V 3
1.4 V to 1.6 V 6
IOL Low-level output current 1.65 V to 1.95 V 8 mA
2.3 V to 2.7 V 9
3 V to 3.6 V 12
Δt/Δv Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature –40 125 °C

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See Implications of Slow or
Floating CMOS Inputs, SCBA004.

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5.4 Thermal Information

SN74AVC8T245
THERMAL METRIC(1) DGV PW RHL UNIT
24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 116.7 93.1 36.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 48.5 36.7 32.5 °C/W
RθJB Junction-to-board thermal resistance 62.1 48.4 15.7 °C/W
ψJT Junction-to-top characterization parameter 7.0 93.1 0.7 °C/W
ψJB Junction-to-board characterization parameter 61.6 48.0 15.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 5.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)(2) (1)
TA = 25°C –40°C to +85°C –40°C to +125°C
PARAMETER TEST CONDITIONS VCCA VCCB UNIT
MIN TYP MAX MIN MAX MIN MAX
VCCO –
IOH = –100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V VCCO – 0.2
0.2
IOH = –3 mA 1.2 V 1.2 V 0.95

VOH IOH = –6 mA VI = VIH 1.4 V 1.4 V 1.05 1 V

IOH = –8 mA 1.65 V 1.65 V 1.2 1.2
IOH = –9 mA 2.3 V 2.3 V 1.75 1.75
IOH = –12 mA 3V 3V 2.3 2.3
IOL = 100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V 0.2 0.2
IOL = 3 mA 1.2 V 1.2 V 0.15
IOL = 6 mA 1.4 V 1.4 V 0.35 0.35
VOL VI = VIL V
IOL = 8 mA 1.65 V 1.65 V 0.45 0.45
IOL = 9 mA 2.3 V 2.3 V 0.55 0.55
IOL = 12 mA 3V 3V 0.7 0.7
Control
II VI = VCCA or GND 1.2 V to 3.6 V 1.2 V to 3.6 V –0.25 ±0.025 0.25 –1 1 ±1 μA
inputs

A or B 0V 0 V to 3.6 V –1 ±0.1 1 –5 5 ±5
Ioff VI or VO = 0 to 3.6 V μA
port 0 V to 3.6 V 0V –1 ±0.1 1 –5 5 ±5
VO = VCCO or GND,
IOZ A or B
(3) VI = VCCI or GND, 3.6 V 3.6 V ±0.5 ±2.5 ±5 ±5 μA
port
OE = VIH
1.2 V to 3.6 V 1.2 V to 3.6 V 15 15
VI = VCCI or
ICCA IO = 0 0V 3.6 V –2 –2 μA
GND,
3.6 V 0V 15 15
1.2 V to 3.6 V 1.2 V to 3.6 V 15 15
VI = VCCI or
ICCB IO = 0 0V 3.6 V 15 15 μA
GND,
3.6 V 0V –2 –2
VI = VCCI or
ICCA + ICCB IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 25 25 μA
GND,
Control
Ci VI = 3.3 V or GND 3.3 V 3.3 V 3.5 4.5 pF
inputs
A or B
Cio VO = 3.3 V or GND 3.3 V 3.3 V 6 7 pF
port

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.
(3) For I/O ports, the parameter IOZ includes the input leakage current.

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5.6 Switching Characteristics, VCCA = 1.2 V

over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) TYP TYP
VCCB = 1.2 V 3.1 3.1
VCCB = 1.5 V 2.6 2.6
tPLH, tPHL A B VCCB = 1.8 V 2.5 2.5 ns
VCCB = 2.5 V 3 3
VCCB = 3.3 V 3.5 3.5
VCCB = 1.2 V 3.1 3.1
VCCB = 1.5 V 2.7 2.7
tPLH, tPHL B A VCCB = 1.8 V 2.5 2.5 ns
VCCB = 2.5 V 2.4 2.4
VCCB = 3.3 V 2.3 2.3
VCCB = 1.2 V
VCCB = 1.5 V
tPZH, tPZL OE A VCCB = 1.8 V 5.3 5.3 ns
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.2 V 5.1 5.1
VCCB = 1.5 V 4 4
tPZH, tPZL OE B VCCB = 1.8 V 3.5 3.5 ns
VCCB = 2.5 V 3.2 3.2
VCCB = 3.3 V 3.1 3.1
VCCB = 1.2 V
VCCB = 1.5 V
tPHZ, tPLZ OE A VCCB = 1.8 V 4.8 4.8 ns
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.2 V 4.7 4.7
VCCB = 1.5 V 4 4
tPHZ, tPLZ OE B VCCB = 1.8 V 4.1 4.1 ns
VCCB = 2.5 V 4.3 4.3
VCCB = 3.3 V 5.1 5.1

5.7 Switching Characteristics, VCCA = 1.5 V ± 0.1 V

over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 2.7 3.1
VCCB = 1.5 V ± 0.1 V 0.5 5.4 0.5 14.7
tPLH, tPHL A B VCCB = 1.8 V ± 0.15 V 0.5 4.6 0.5 13.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.9 0.5 13.9
VCCB = 3.3 V ± 0.3 V 0.5 6.8 0.5 17.2

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5.7 Switching Characteristics, VCCA = 1.5 V ± 0.1 V (continued)

over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 2.6 3.1
VCCB = 1.5 V ± 0.1 V 0.5 5.4 0.5 14.7
tPLH, tPHL B A VCCB = 1.8 V ± 0.15 V 0.5 5.1 0.5 14.2 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.7 0.5 13.5
VCCB = 3.3 V ± 0.3 V 0.5 4.5 0.5 13.2
VCCB = 1.2 V 3.7 5.3
VCCB = 1.5 V ± 0.1 V 1.1 8.7 0.5 20.5
tPZH, tPZL OE A VCCB = 1.8 V ± 0.15 V 1.1 8.7 0.5 20.5 ns
VCCB = 2.5 V ± 0.2 V 1.1 8.7 0.5 20.5
VCCB = 3.3 V ± 0.3 V 1.1 8.7 0.5 20.5
VCCB = 1.2 V 4.8 5.1
VCCB = 1.5 V ± 0.1 V 1.1 7.6 0.5 18.6
tPZH, tPZL OE B VCCB = 1.8 V ± 0.15 V 1.1 7.1 0.5 17.7 ns
VCCB = 2.5 V ± 0.2 V 1 5.6 0.5 15.1
VCCB = 3.3 V ± 0.3 V 1 5.2 0.5 14.4
VCCB = 1.2 V 3.1 4.8
VCCB = 1.5 V ± 0.1 V 0.5 8.6 0.5 20.3
tPHZ, tPLZ OE A VCCB = 1.8 V ± 0.15 V 0.5 8.6 0.5 20.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 8.6 0.5 20.3
VCCB = 3.3 V ± 0.3 V 0.5 8.6 0.5 20.3
VCCB = 1.2 V 4.1 4.7
VCCB = 1.5 V ± 0.1 V 0.5 8.4 0.5 20
tPHZ, tPLZ OE B VCCB = 1.8 V ± 0.15 V 0.5 7.6 0.5 18.6 ns
VCCB = 2.5 V ± 0.2 V 0.5 7.2 0.5 17.9
VCCB = 3.3 V ± 0.3 V 0.5 7.8 0.5 18.9

5.8 Switching Characteristics, VCCA = 1.8 V ± 0.15 V

over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 2.5 2.5
VCCB = 1.5 V ± 0.1 V 0.5 5.1 0.5 14.2
tPLH, tPHL A B VCCB = 1.8 V ± 0.15 V 0.5 4.4 0.5 13 ns
VCCB = 2.5 V ± 0.2 V 0.5 4 0.5 12.3
VCCB = 3.3 V ± 0.3 V 0.5 3.9 0.5 12.1
VCCB = 1.2 V 2.5 2.5
VCCB = 1.5 V ± 0.1 V 0.5 4.6 0.5 13.3
tPLH, tPHL B A VCCB = 1.8 V ± 0.15 V 0.5 4.4 0.5 13 ns
VCCB = 2.5 V ± 0.2 V 0.5 3.9 0.5 12.1
VCCB = 3.3 V ± 0.3 V 0.5 3.7 0.5 11.8

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5.8 Switching Characteristics, VCCA = 1.8 V ± 0.15 V (continued)

over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 3 3
VCCB = 1.5 V ± 0.1 V 1 6.8 0.5 17.2
tPZH, tPZL OE A VCCB = 1.8 V ± 0.15 V 1 6.8 0.5 17.2 ns
VCCB = 2.5 V ± 0.2 V 1 6.8 0.5 17.2
VCCB = 3.3 V ± 0.3 V 1 6.8 0.5 17.2
VCCB = 1.2 V 4.6 4.6
VCCB = 1.5 V ± 0.1 V 1.1 8.2 0.5 19.6
tPZH, tPZL OE B VCCB = 1.8 V ± 0.15 V 1 6.7 0.5 17 ns
VCCB = 2.5 V ± 0.2 V 0.5 5.1 0.5 14.2
VCCB = 3.3 V ± 0.3 V 0.5 4.5 0.5 13.2
VCCB = 1.2 V 2.8 2.8
VCCB = 1.5 V ± 0.1 V 0.5 7.1 0.5 17.7
tPHZ, tPLZ OE A VCCB = 1.8 V ± 0.15 V 0.5 7.1 0.5 17.7 ns
VCCB = 2.5 V ± 0.2 V 0.5 7.1 0.5 17.7
VCCB = 3.3 V ± 0.3 V 0.5 7.1 0.5 17.7
VCCB = 1.2 V 3.9 3.9
VCCB = 1.5 V ± 0.1 V 0.5 7.8 0.5 18.9
tPHZ, tPLZ OE B VCCB = 1.8 V ± 0.15 V 0.5 6.9 0.5 17.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 6 0.5 15.8
VCCB = 3.3 V ± 0.3 V 0.5 5.8 0.5 15.4

5.9 Switching Characteristics, VCCA = 2.5 V ± 0.2 V

over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 2.4 2.4
VCCB = 1.5 V ± 0.1 V 0.5 4.7 0.5 13.5
tPLH, tPHL A B VCCB = 1.8 V ± 0.15 V 0.5 3.9 0.5 12.1 ns
VCCB = 2.5 V ± 0.2 V 0.5 3.1 0.5 10.7
VCCB = 3.3 V ± 0.3 V 0.5 2.8 0.5 10.2
VCCB = 1.2 V 3 3
VCCB = 1.5 V ± 0.1 V 0.5 4.9 0.5 13.9
tPLH, tPHL B A VCCB = 1.8 V ± 0.15 V 0.5 4 0.5 12.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 3.1 0.5 10.7
VCCB = 3.3 V ± 0.3 V 0.5 2.9 0.5 10.4
VCCB = 1.2 V 2.2 2.2
VCCB = 1.5 V ± 0.1 V 0.5 4.8 0.5 13.7
tPZH, tPZL OE A VCCB = 1.8 V ± 0.15 V 0.5 4.8 0.5 13.7 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.8 0.5 13.7
VCCB = 3.3 V ± 0.3 V 0.5 4.8 0.5 13.7

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5.9 Switching Characteristics, VCCA = 2.5 V ± 0.2 V (continued)

over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 4.5 4.5
VCCB = 1.5 V ± 0.1 V 1.1 7.9 0.5 19.1
tPZH, tPZL OE B VCCB = 1.8 V ± 0.15 V 0.5 6.4 0.5 16.5 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.6 0.5 13.3
VCCB = 3.3 V ± 0.3 V 0.5 4 0.5 12.3
VCCB = 1.2 V 1.8 1.8
VCCB = 1.5 V ± 0.1 V 0.5 5.1 0.5 14.2
tPHZ, tPLZ OE A VCCB = 1.8 V ± 0.15 V 0.5 5.1 0.5 14.2 ns
VCCB = 2.5 V ± 0.2 V 0.5 5.1 0.5 14.2
VCCB = 3.3 V ± 0.3 V 0.5 5.1 0.5 14.2
VCCB = 1.2 V 3.6 3.6
VCCB = 1.5 V ± 0.1 V 0.5 7.1 0.5 17.7
tPHZ, tPLZ OE B VCCB = 1.8 V ± 0.15 V 0.5 6.3 0.5 16.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 5.1 0.5 14.2
VCCB = 3.3 V ± 0.3 V 0.5 3.9 0.5 12.1

5.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 2.3 2.3
VCCB = 1.5 V ± 0.1 V 0.5 4.5 0.5 13.2

VCCB = 1.8 tPLH 0.5 3.7 0.5 11.1

tPLH, tPHL A B ns
V ± 0.15 V tPHL 0.5 3.3 0.5 11.1
VCCB = 2.5 V ± 0.2 V 0.5 2.9 0.5 10.4
VCCB = 3.3 V ± 0.3 V 0.5 2.5 0.5 9.7
VCCB = 1.2 V 3.5 3.5
VCCB = 1.5 V ± 0.1 V 0.5 6.8 0.5 17.2
tPLH, tPHL B A VCCB = 1.8 V ± 0.15 V 0.5 3.9 0.5 12.1 ns
VCCB = 2.5 V ± 0.2 V 0.5 2.8 0.5 10.2
VCCB = 3.3 V ± 0.3 V 0.5 2.5 0.5 9.7
VCCB = 1.2 V 2 2
VCCB = 1.5 V ± 0.1 V 0.5 4 0.5 12.3
tPZH, tPZL OE A VCCB = 1.8 V ± 0.15 V 0.5 4 0.5 12.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 4 0.5 12.3
VCCB = 3.3 V ± 0.3 V 0.5 4 0.5 12.3
VCCB = 1.2 V 4.5 4.5
VCCB = 1.5 V ± 0.1 V 1.1 7.8 0.5 18.9
tPZH, tPZL OE B VCCB = 1.8 V ± 0.15 V 0.5 6.2 0.5 16.1 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.5 0.5 13.2
VCCB = 3.3 V ± 0.3 V 0.5 3.9 0.5 12.3

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5.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V (continued)

over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 6-1)
FROM TO TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER VCCB UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
VCCB = 1.2 V 1.7 1.7
VCCB = 1.5 V ± 0.1 V 0.5 4 0.5 12.3
tPHZ, tPLZ OE A VCCB = 1.8 V ± 0.15 V 0.5 4 0.5 12.3 ns
VCCB = 2.5 V ± 0.2 V 0.5 4 0.5 12.3
VCCB = 3.3 V ± 0.3 V 0.5 4 0.5 12.3
VCCB = 1.2 V 3.4 3.4
VCCB = 1.5 V ± 0.1 V 0.5 6.9 0.5 17.4
tPHZ, tPLZ OE B VCCB = 1.8 V ± 0.15 V 0.5 6 0.5 15.8 ns
VCCB = 2.5 V ± 0.2 V 0.5 4.8 0.5 13.7
VCCB = 3.3 V ± 0.3 V 0.5 4.2 0.5 12.6

5.11 Operating Characteristics

TA = 25°C
VCCA = VCCA = VCCA = VCCA = VCCA =
TEST VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
PARAMETER UNIT
CONDITIONS
TYP TYP TYP TYP TYP
Outputs
1 1 1 1 1
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdA (1) f = 10 MHz, pF
Outputs tr = tf = 1 ns 12 12 12 13 14
enabled
B to A
Outputs
1 1 1 1 1
disabled
Outputs
12 12 12 13 14
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdB (1) f = 10 MHz, pF
Outputs tr = tf = 1 ns 1 1 1 1 1
enabled
B to A
Outputs
1 1 1 1 1
disabled

(1) Power dissipation capacitance per transceiver

5.12 Typical Total Static Power Consumption (ICCA + ICCB)

VCCA
VCCB UNIT
0V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
0V 0 <0.5 <0.5 <0.5 <0.5 <0.5
1.2 V <0.5 <1 <1 <1 <1 1
1.5 V <0.5 <1 <1 <1 <1 1
µA
1.8 V <0.5 <1 <1 <1 <1 <1
2.5 V <0.5 1 <1 <1 <1 <1
3.3 V <0.5 1 <1 <1 <1 <1

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5.13 Typical Characteristics

TA = 25°C

6 6

5 5
Typical Propagation Delay (ns)

Typical Propagation Delay (ns)

4 4

3 3

2 VCCB = 1.2 V 2 VCCB = 1.2 V

VCCB = 1.5 V VCCB = 1.5 V
VCCB = 1.8 V VCCB = 1.8 V
1 1
VCCB = 2.5 V VCCB = 2.5 V
VCCB = 3.3 V VCCB = 3.3 V

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Load Capacitance (pF) Load Capacitance (pF)

VCCA = 1.2 V VCCA = 1.5 V

Figure 5-1. Typical Propagation Delay (A to B) vs Load Figure 5-2. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance
6 6
VCCB = 1.2 V
VCCB = 1.5 V
5 5
VCCB = 1.8 V
Typical Propagation Delay (ns)

Typical Propagation Delay (ns)

VCCB = 2.5 V
4 4 VCCB = 3.3 V

3 3

2 VCCB = 1.2 V 2
VCCB = 1.5 V
VCCB = 1.8 V
1 1
VCCB = 2.5 V
VCCB = 3.3 V

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Load Capacitance (pF) Load Capacitance (pF)
VCCA = 1.5 V VCCA = 1.8 V
Figure 5-3. Typical Propagation Delay (A to B) vs Load Figure 5-4. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance
6 6
VCCB = 1.2 V VCCB = 1.2 V
VCCB = 1.5 V VCCB = 1.5 V
5 5
VCCB = 1.8 V
Typical Propagation Delay (ns)
Typical Propagation Delay (ns)

VCCB = 1.8 V
VCCB = 2.5 V VCCB = 2.5 V
4 VCCB = 3.3 V 4 VCCB = 3.3 V

3 3

2 2

1 1

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60

Load Capacitance (pF) Load Capacitance (pF)

VCCA = 1.8 V VCCA = 2.5 V

Figure 5-5. Typical Propagation Delay (A to B) vs Load Figure 5-6. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance

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5.13 Typical Characteristics (continued)

TA = 25°C

6 6
VCCB = 1.2 V VCCB = 1.2 V
VCCB = 1.5 V VCCB = 1.5 V
5 5
Typical Propagation Delay (ns)

VCCB = 1.8 V

Typical Propagation Delay (ns)

VCCB = 1.8 V
VCCB = 2.5 V VCCB = 2.5 V
4 VCCB = 3.3 V 4 VCCB = 3.3 V

3 3

2 2

1 1

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Load Capacitance (pF) Load Capacitance (pF)

VCCA = 2.5 V VCCA = 3.3 V

Figure 5-7. Typical Propagation Delay (A to B) vs Load Figure 5-8. Typical Propagation Delay (A to B) vs Load
Capacitance Capacitance

6
VCCB = 1.2 V
VCCB = 1.5 V
5
VCCB = 1.8 V
Typical Propagation Delay (ns)

VCCB = 2.5 V
4 VCCB = 3.3 V

0
0 10 20 30 40 50 60
Load Capacitance (pF)

VCCA = 3.3 V
Figure 5-9. Typical Propagation Delay (A to B) vs Load Capacitance

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Parameter Measurement Information

2 × VCCO
TEST S1
RL S1 Open tpd Open
From Output
GND tPLZ/tPZL 2 × VCCO
Under Test
tPHZ/tPZH GND
CL RL
(see Note A)

LOAD CIRCUIT tw

VCCI
Input VCCI/2 VCCI/2
VCCO CL RL VTP 0V
1.2 V 15 pF 2 kW 0.1 V
VOLTAGE WAVEFORMS
1.5 V ± 0.1 V 15 pF 2 kW 0.1 V PULSE DURATION
1.8 V ± 0.15 V 15 pF 2 kW 0.15 V
2.5 V ± 0.2 V 15 pF 2 kW 0.15 V
3.3 V ± 0.3 V 15 pF 2 kW 0.3 V VCCA
Output
Control VCCA/2 VCCA/2
(low-level
enabling) 0V

tPZL tPLZ

Output VCCO
VCCI
Input VCCI/2 VCCI/2 Waveform 1 VCCO/2 VOL + VTP
S1 at 2 × VCCO VOL
0V
(see Note B)
tPLH tPHL tPZH tPHZ
Output
VOH
VOH Waveform 2 VOH − VTP
S1 at GND VCCO/2
Output VCCO/2 VCCO/2
(see Note B) 0V
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.

Figure 6-1. Load Circuit and Voltage Waveforms

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6 Detailed Description
6.1 Overview
The SN74AVC8T245 is an 8-bit, dual-supply noninverting transceiver with bidirectional voltage level translation.
VCCA supports pins A and the control pins (DIR and OE), and VCCB supports pins B. The A port is able to accept
I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on
DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set
to low. When OE is set to high, both A and B are in the high-impedance state.
6.2 Functional Block Diagram

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

6.3 Feature Description

6.3.1 Fully Configurable Dual-Rail Design
The fully configurable dual-rail design allows each port to operate over the full 1.2-V to 3.6-V power-supply
range. Both VCCA and VCCB can be supplied at any voltage between 1.2 V and 3.6 V making the device an
excellent choice for translating between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).
6.3.2 Support High-Speed Translation
SN74AVC8T245 can support high data rate application. The translated signal data rate can be up to 320Mbps
when the device power supply is more than 1.8 V.
6.3.3 Ioff Supports Partial-Power-Down Mode Operation
Ioff prevents backflow current by disabling I/O output circuits when device is in partial power-down mode. The
inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
6.3.4 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. Two outputs can be connected together for 2X stronger output drive strength. The electrical and
thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
6.3.5 Vcc Isolation
The I/Os of both ports will enter a high-impedance state when one of the supplies are at GND, while the other
supply is still connected to the device (IOZ shown in Electrical Characteristics).

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6.4 Device Functional Modes

The SN74AVC8T245 is a voltage level transceiver that can operate from 1.2 V to 3.6 V (VCCA) and 1.2 V to 3.6
V (VCCB). The signal translation between 1.2 V and 3.6 V requires direction control and output enable control.
When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data
transmission is from B to A. When OE is high, both output ports will be high-impedance.
Table 6-1. Function Table
(Each 8-Bit Section)
INPUTS
OPERATION
OE DIR
L L B data to A
bus
L H A data to B
bus
H X All outputs Hi-
Z

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The SN74AVC8T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AVC8T245 device is an excellent choice
for data transmission when direction is different. It is recommended to tie all unused I/Os to GND. The device
should not have any floating I/Os when changing translation direction. The maximum data rate can be up to
320Mbps when device voltage power supply is more than 1.8 V.
7.2 Typical Application
1.2V 3.3V

0.1 µF 0.1 µF 1 µF

VCCA VCCB

DIR

OE

1.2 V 3.3 V
SN74AVC8T245
Controller System

A1 B1
A2 B2
A3 B3
A4 B4
Data Data
A5 B5
A6 B6
A7 B7
A8 B8

GND GND GND

Figure 7-1. Typical Application Schematic

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7.2.1 Design Requirements

For this design example, use the parameters listed in Table 7-1.
Table 7-1. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUE
Input voltage range 1.2 V to 3.6 V
Output voltage range 1.2 V to 3.6 V

7.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AVC8T245 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AVC8T245 device is driving to determine the output
voltage range.
7.2.3 Application Curve

1.2V to 3.3V Voltage Translation(2.5MHz)

Input(1.2V)

Output(3.3V)

Figure 7-2. Translation Up (1.2 V to 3.3 V) at 2.5 MHz

7.3 Power Supply Recommendations

The SN74AVC8T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port
and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation
between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V voltage nodes. The recommendation is to first power-up
the input supply rail to help avoid internal floating while the output supply rail ramps up. However, both power-
supply rails can be ramped up simultaneously.
The output-enable OE input circuit is designed so that it is supplied by VCCA and when the OE input is high, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by
the current-sinking capability of the driver.
7.4 Layout
7.4.1 Layout Guidelines
For device reliability, follow common printed-circuit board layout guidelines such as:
• Use bypass capacitors on power supplies.
• Use short trace lengths to avoid excessive loading.
• Place pads on the signal paths for loading capacitors or pullup resistors to adjust the signals rise and fall
times, depending on the system requirements.

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7.4.2 Layout Example

LEGEND

VIA to Power Plane Polygonal Copper Pour

VIA to GND Plane (Inner Layer)

VCCA VCCB

Bypass Capacitor Bypass Capacitor

VCCA

1 VCCA VCCB 16

Keep OE high until VCCA and

2 DIR VCCB 15 VCCB are powered up

From
3 A1 OE 14
Controller

From To
4 A2 B1 13 System
Controller

From To
5 A3 B2 12 System
Controller

From To
6 A4 B3 11 System
Controller

From To
7 A5 B4 10 System
Controller

From To
8 A6 B5 12 System
Controller

From To
9 A7 B6 11 System
Controller

From To
10 A8 B7 10 System
Controller

To
11 GND B8 10 System

12 GND GND 13

SN74AVC8T245

Figure 7-3. SN74AVC8T245 Layout Example

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8 Device and Documentation Support

8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2017) to Revision K (November 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated the Package Information table to include package lead size............................................................... 1
• Updated the Thermal Information table for all packages....................................................................................6

Changes from Revision I (December 2014) to Revision J (March 2017) Page

• Changed MAX value for Operating free-air temperature, TA from: 85°C to: 125°C........................................... 5
• Added values for TA = –40°C to +125°C in Electrical Characteristics and all Switching Characteristics tables.6
• Added Documentation Support section, Receiving Notification of Documentation Updates, and Community
Resources section............................................................................................................................................ 20

Changes from Revision H (February 2007) to Revision I (December 2014) Page

• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

74AVC8T245RHLRG4 Active Production VQFN (RHL) | 24 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 WE245
SN74AVC8T245DGVR Active Production TVSOP (DGV) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245DGVR.Z Active Production TVSOP (DGV) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245DGVRG4.Z Active Production TVSOP (DGV) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PW Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PW.Z Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWE4 Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWG4 Active Production TSSOP (PW) | 24 60 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWR.Z Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWRE4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245PWRG4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 WE245
SN74AVC8T245RHLR Active Production VQFN (RHL) | 24 1000 | LARGE T&R Yes NIPDAU | NIPDAU Level-2-260C-1 YEAR -40 to 125 WE245
SN74AVC8T245RHLR.Z Active Production VQFN (RHL) | 24 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 WE245

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2025

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AVC8T245 :

• Automotive : SN74AVC8T245-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVC8T245DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AVC8T245PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74AVC8T245RHLR VQFN RHL 24 1000 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AVC8T245DGVR TVSOP DGV 24 2000 356.0 356.0 35.0
SN74AVC8T245PWR TSSOP PW 24 2000 356.0 356.0 35.0
SN74AVC8T245RHLR VQFN RHL 24 1000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74AVC8T245PW PW TSSOP 24 60 530 10.2 3600 3.5
SN74AVC8T245PW.Z PW TSSOP 24 60 530 10.2 3600 3.5
SN74AVC8T245PWE4 PW TSSOP 24 60 530 10.2 3600 3.5
SN74AVC8T245PWG4 PW TSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
DGV0024A SCALE 2.500
TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6
TYP
A 6.2
PIN 1 INDEX 0.08 C SEATING
AREA 22X 0.4 PLANE
24
1

2X
5.1
4.4
4.9
NOTE 3

12
13
0.23
24X
4.5 0.13
B
4.3 0.07 C A B
NOTE 4

(0.15) TYP
SEE DETAIL A 0.25
GAGE PLANE 1.2 MAX

0.75 0.15
0 -8 0.50 0.05

DETAIL A
A 15

TYPICAL

4229221/A 12/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGV0024A TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.4)
24X (0.2) SYMM
1
24

22X (0.4)

SYMM

(R0.05) TYP

12 13

(5.9)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

SOLDER MASK METAL UNDER SOLDER MASK

METAL EDGE
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN
ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4229221/A 12/2022
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGV0024A TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.4) SYMM

24X (0.2)
1
24

22X (0.4)

SYMM

(R0.05) TYP

12 13

(5.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 12X

4229221/A 12/2022
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RGY 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.5 x 3.5 mm, 0.5 mm pitch

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4203539-5/J
 PACKAGE OUTLINE
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
3.6 A
B 3.4

PIN 1 INDEX AREA

5.6
5.4

1 MAX
C

SEATING PLANE
0.05
0.00 2.05±0.1 0.08 C
2X 1.5

24X 0.5
SYMM
0.3 (0.1) TYP
12 13
18X 0.5
11
14

21

2X SYMM
4.05±0.1
4.5

23
2
24X 0.30
0.18
PIN 1 ID 1 24
0.1 C A B
(OPTIONAL) 4X (0.2)
2X (0.55) 0.05 C
4225250/B 12/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1 24
24X (0.6)

24X (0.24) 2X (0.4)

23
2

18X (0.5)

2X (1.105)

25 6X (0.67)

SYMM 4.6
(4.05) (5.3)
4.4

SOLDER MASK
OPENING

METAL UNDER
SOLDER MASK

(Ø 0.2) VIA
TYP

(R0.05) TYP
11
14

12 13

4X
(0.775)
4X (0.2)

2X (0.55)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN SOLDER MASK
0.07 MAX OPENING
ALL AROUND ALL AROUND

EXPOSED METAL EXPOSED METAL

METAL

SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED) 4225250/B 12/2024
SOLDER MASK DETAILS
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RHL0024A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(3.3)
(2.05)
2X (1.5)
SYMM
SOLDER MASK EDGE
1 24 TYP
24X (0.6)

24X (0.24)

2 23

18X (0.5)

25

SYMM 4.6 (5.3)

4.4

4X
(1.34)

METAL TYP

(R0.05) TYP
11
14

12 13 2X (0.84)
6X (0.56)
4X (0.2)

2X (0.55)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 18X

4225250/B 12/2024

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
PW0024A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1

2X
7.9 7.15
7.7
NOTE 3

12
13
0.30
24X
4.5 0.19 1.2 MAX
B
4.3 0.1 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

1 (R0.05) TYP

24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220208/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

(R0.05) TYP
1
24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220208/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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