TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

www.ti.com SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

FEATURES • Twelve Communication Interfaces:

• High-Performance Static CMOS Technology – Two Serial Peripheral Interfaces (SPIs)
• TMS470R1x 16/32-Bit RISC Core – 255 Programmable Baud Rates
(ARM7TDMI™) – Three Serial Communication Interfaces
– 60-MHz System Clock (Pipeline Mode) (SCIs)
– Independent 16/32-Bit Instruction Set • 224 Selectable Baud Rates
– Open Architecture With Third-Party Support • Asynchronous/Isosynchronous Modes
– Built-In Debug Module – Two High-End CAN Controllers (HECC)
• Integrated Memory • 32-Mailbox Capacity
– 1M-Byte Program Flash • Fully Compliant With CAN Protocol,
• Two Banks With 16 Contiguous Sectors Version 2.0B
– 64K-Byte Static RAM (SRAM) – Five Inter-Integrated Circuit (I2C) Modules
– Memory Security Module (MSM) • Multi-Master and Slave Interfaces
– JTAG Security Module • Up to 400 Kbps (Fast Mode)
• Operating Features • 7- and 10-Bit Address Capability
– Low-Power Modes: STANDBY and HALT • High-End Timer Lite (HET)
– Industrial Temperature Range – 12 Programmable I/O Channels:
• 470+ System Module • 12 High-Resolution Pins
– 32-Bit Address Space Decoding – High-Resolution Share Feature (XOR)
– Bus Supervision for Memory/Peripherals – High-End Timer RAM
– Digital Watchdog (DWD) Timer • 64-Instruction Capacity
– Analog Watchdog (AWD) Timer • External Clock Prescale (ECP) Module
– Enhanced Real-Time Interrupt (RTI) – Programmable Low-Frequency External
– Interrupt Expansion Module (IEM) Clock (CLK)
– System Integrity and Failure Detection • 12-Channel, 10-Bit Multi-Buffered ADC
(MibADC)
– ICE Breaker
– 64-Word FIFO Buffer
• Direct Memory Access (DMA) Controller
– Single- or Continuous-Conversion Modes
– 32 Control Packets and 16 Channels
– 1.55 µs Minimum Sample and Conversion
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Time
Clock Module With Prescaler
– Calibration Mode and Self-Test Features
– Multiply-by-4 or -8 Internal ZPLL Option
• Flexible Interrupt Handling
– ZPLL Bypass Mode
• Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
• 46 Dedicated General-Purpose I/O (GIO) Pins
and 47 Additional Peripheral I/Os
• Sixteen External Interrupts
• On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller www.ti.com
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

• 144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)
(1) The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.

TMS470R1B1M 144-Pin PGE Package Without Expansion Bus (Top View)

GIOF[7]/INT[15]
GIOF[6]/INT[14]

GIOF[5]/INT[13]

GIOF[4]/INT[12]

GIOF[2]/INT[10]
GIOF[3]/INT[11]
GIOA[5]/INT[5]

GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOF[1]/INT[9]

GIOF[0]/INT[8]
CAN1HRX
CAN1HTX
ADIN[10]

I2C2SDA

I2C1SDA

CLKOUT
ADIN[11]

I2C2SCL

I2C1SCL

GIOE[7]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]

PLLDIS
ADEVT

HET[0]
VCCIO
VSSIO

TDO
TCK
VCC
VSS

TDI
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
ADREFHI 109 72 HET[1]
ADREFLO 110 71 HET[2]
VCCAD 111 70 GIOE[6]
VSSAD 112 69 VCCIO
ADIN[4] 113 68 VSSIO
ADIN[3] 114 67 GIOE[5]
ADIN[2] 115 66 HET[3]
ADIN[1] 116 65 HET[4]
ADIN[0] 117 64 GIOE[4]
PORRST 118 63 HET[5]
GIOC[4] 119 62 SPI2SCS
GIOC[3] 120 61 GIOE[3]
RST 121 60 SPI2ENA
VSS 122 59 SPI2SIMO
VCC 123 58 GIOE[2]
TEST 124 57 SPI2SOMI
GIOH[5] 125 56 SPI2CLK
GIOC[2] 126 55 CAN2HTX
GIOA[4]/INT[4] 127 54 CAN2HRX
GIOC[1] 128 53 VCC
VSS 129 52 VSS
VCC 130 51 SCI2CLK
VCCP 131 50 SCI2RX
FLTP2 132 49 SCI2TX
GIOA[3]/INT[3] 133 48 SCI1CLK
GIOA[2]/INT[2] 134 47 GIOE[1]
GIOC[0] 135 46 SCI1RX
GIOA[1]/INT[1]/ECLK 136 45 SCI1TX
VCCIO 137 44 GIOE[0]
VSSIO 138 43 GIOB[0]
GIOH[0] 139 42 GIOD[0]
GIOG[7] 140 41 I2C4SDA
GIOA[0]/INT[0] 141 40 I2C4SCL
GIOG[6] 142 39 GIOD[1]
GIOG[5] 143 38 I2C5SDA
TRST 144 37 I2C5SCL
10

12
13
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30
31
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35
36
11
1
2
3
4
5
6
7
8
9
SPI1SCS
SPI1ENA

SCI3RX
SPI1CLK

SCI3TX

I2C3SDA
SPI1SIMO

SPI1SOMI

TMS2

SCI3CLK
TMS
VCC

VCC
HET[6]

HET[7]
HET[8]

I2C3SCL
VSS

VSS
OSCOUT

AWD
OSCIN
HET[18]

HET[20]
HET[22]
GIOG[4]

GIOG[3]

GIOG[2]

GIOG[1]

GIOG[0]

VCCIO
VSSIO
GIOD[5]

GIOD[4]

GIOD[3]

GIOD[2]

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16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

TMS470R1B1M 144-Pin PGE Package With Expansion Bus (Top View)

EBADDR[13]/EBDATA[15]
EBADDR[12]/EBDATA[14]

EBADDR[10]/EBDATA[12]
EBADDR[11]/EBDATA[13]

EBADDR[8]/EBDATA[10]
EBADDR[9]/EBDATA[11]

EBADDR[7]/EBDATA[9]

EBADDR[6]/EBDATA[8]
GIOA[5]/INT[5]

GIOA[7]/INT[7]
GIOA[6]/INT[6]
EBDATA[7]
CAN1HRX
CAN1HTX
ADIN[10]

I2C2SDA

I2C1SDA

CLKOUT
ADIN[11]

I2C2SCL

I2C1SCL
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]

PLLDIS
ADEVT

HET[0]
VCCIO
VSSIO

TDO
TCK
VCC
VSS

TDI
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
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83
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73
ADREFHI 109 72 HET[1]
ADREFLO 110 71 HET[2]
VCCAD 111 70 EBDATA[6]
VSSAD 112 69 VCCIO
ADIN[4] 113 68 VSSIO
ADIN[3] 114 67 EBDATA[5]
ADIN[2] 115 66 HET[3]
ADIN[1] 116 65 HET[4]
ADIN[0] 117 64 EBDATA[4]
PORRST 118 63 HET[5]
EBCS[6] 119 62 SPI2SCS
EBCS[5] 120 61 EBDATA[3]
RST 121 60 SPI2ENA
VSS 122 59 SPI2SIMO
VCC 123 58 EBDATA[2]
TEST 124 57 SPI2SOMI
EBHOLD 125 56 SPI2CLK
EBWR[1] 126 55 CAN2HTX
GIOA[4]/INT[4] 127 54 CAN2HRX
EBWR[0] 128 53 VCC
VSS 129 52 VSS
VCC 130 51 SCI2CLK
VCCP 131 50 SCI2RX
FLTP2 132 49 SCI2TX
GIOA[3]/INT[3] 133 48 SCI1CLK
GIOA[2]/INT[2] 134 47 EBDATA[1]
EBOE 135 46 SCI1RX
GIOA[1]/INT[1]/ECLK 136 45 SCI1TX
VCCIO 137 44 EBDATA[0]
VSSIO 138 43 EBDMAREQ[0]
EBADDR[22]/EBADDR[14] 139 42 EBADDR[0]
EBADDR[21]/EBADDR[13] 140 41 EBADDR[23]/EBADDR[15]
GIOA[0]/INT[0] 141 40 EBADDR[24]/EBADDR[16]
EBADDR[20]/EBADDR[12] 142 39 EBADDR[1]
EBADDR[19]/EBADDR[11] 143 38 EBADDR[26]/EBADDR[18]
TRST 144 37 EBADDR[25]/EBADDR[17]
10

12
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11
1
2
3
4
5
6
7
8
9
SPI1ENA
SPI1SCS

SPI1SIMO

SPI1SOMI

SCI3CLK
TMS
EBADDR[18]/EBADDR[10]

SCI3RX
SPI1CLK

EBADDR[17]/EBADDR[9]

EBADDR[16]/EBADDR[8]

VCC
EBADDR[15]/EBADDR[7]

EBADDR[14]/EBADDR[6]
SCI3TX

I2C3SDA

VCC
I2C3SCL
TMS2

OSCOUT

AWD
OSCIN
HET[18]

HET[20]
HET[22]
HET[6]

HET[7]
HET[8]

VSS

VSS
VCCIO
VSSIO
EBADDR[5]

EBADDR[4]

EBADDR[3]

EBADDR[2]

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TMS470R1B1M
16/32-Bit RISC Flash Microcontroller www.ti.com
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

DESCRIPTION
The TMS470R1B1M (1) devices are members of the Texas Instruments TMS470R1x family of general-purpose
16/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B1M utilizes the big-endian
format where the most significant byte of a word is stored at the lowest numbered byte and the least significant
byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The B1M RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The B1M devices contain the following:
• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 1M-byte flash
• 64K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Digital watchdog (DWD) timer
• Analog watchdog (AWD) timer
• Enhanced real-time interrupt ( RTI) module
• Interrupt expansion module (IEM)
• Memory security module (MSM)
• JTAG security module
• Two serial peripheral interface (SPI) modules
• Three serial communications interface (SCI) modules
• Two high-end CAN controllers (HECC)
• Five inter-integrated circuit (I2C) modules
• 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
• High-end timer lite (HET) controlling 12 I/Os
• External clock prescale (ECP)
• Expansion bus module (EBM)
• Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
The enhanced real-time interrupt (RTI) module on the B1M has the option to be driven by the oscillator clock.
The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral
select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the
SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.

(1) Throughout the remainder of this document, the TMS470R1B1M will be referred to as either the full device name or as B1M.

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16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30
MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency
of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see the
F05 Flash section of this data sheet.
The memory security module (MSM) and the JTAG security module prevent unauthorized access and visibility to
on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.
The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The
SPI provides a convenient method of serial interaction for high-speed communications between similar
shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous
communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The
HECC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control
with robust communication rates of up to 1 megabit per second (Mbps). These CAN peripherals are ideal for
applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial
communication or multiplexed wiring. The I2C module is a multi-master communication module providing an
interface between the B1M microcontroller and an I2C-compatible device via the I2C serial bus. The I2C
supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and
CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197).
For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference
Guide (literature number SPNU223).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For
more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).

NOTE:
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).

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SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

Device Characteristics
Table 1 identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.

Table 1. Device Characteristics

DEVICE DESCRIPTION
CHARACTERISTICS COMMENTS
TMS470R1B1M
MEMORY
For the number of memory selects on this device, see Table 3, TMS470R1B1M Memory Selection Assignment.
Pipeline/Non-Pipeline Flash is pipeline-capable.
1M-Byte flash The B1M RAM is implemented in one 64K array selected by two
INTERNAL MEMORY 64K-Byte SRAM memory-select signals (see Table 3, TMS470R1B1M Memory
Memory Security Module (MSM) Selection Assignment ).
JTAG Security Module
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 6, Interrupt Priority. And for the 1K peripheral address ranges and their
peripheral selects, see Table 4, B1M Peripherals, System Module, and Flash Base Addresses.
CLOCK ZPLL Zero-pin PLL has no external loop filter pins.
Expansion Bus Expansion bus module with 42 pins. Supports 8- and 16-bit
EBM
memories. See Table 7 for details.
GENERAL-PURPOSE I/Os Port A has 8 external pins; Port B has only 1 external pin; Port C
46 I/O has 5 external pins; Port D has 6 external pins; Ports E, F, and G
each have 8 external pins; and Port H has 2 external pins.
ECP YES
SCI 3 (3-pin)
CAN (HECC and/or SCC) 2 HECC Two high-end CAN controllers
SPI (5-pin, 4-pin or 3-pin) 2 (5-pin)
I2C 5
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
HET with XOR Share 12 I/O externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number SPNU199).
HET RAM 64-Instruction Capacity
10-bit, 12-channel Both the logic and registers for a full 16-channel MibADC are
MibADC
64-word FIFO present.
CORE VOLTAGE 1.8 V
I/O VOLTAGE 3.3 V
PINS 144
PACKAGES PGE

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16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

Functional Block Diagram

External External
Pins Pins

Crystal
FLASH Memory OSCIN
VCCP RAM
(1M Byte) Security ZPLL OSCOUT
2 Banks Module (64K Bytes)
FLTP2 PLLDIS
16 Sectors (MSM)
ADIN[11:0]
CPU Address Data Bus ADEVT
MibADC
64−Word ADREFHI
FIFO ADREFLO
TRST
VCCAD
TCK TMS470R1x CPU VSSAD
TDI
TDO HET
ICE Breaker HET[0:8;18,20,22]
TMS 64 Words

Expansion Address/Data Bus

TMS2
CAN1HTX
RST HECC1
CAN1HRX
AWD TMS470R1x System Module
TEST with Enhanced RTI Module(A) CAN2HTX
HECC2
PORRST CAN2SRX
CLKOUT DMA Controller Interrupt Expansion
16 Channels Module (IEM) SCI1CLK
SCI1 SCI1TX
SCC
SCI1RX

I2C4SDA Digital Analog SCI2CLK

I2C4 Watchdog Watchdog
I2C4SCL (DWD) (AWD) SCI2 SCI2TX
SCI2RX
I2C5SDA
I2C5
I2C5SCL I2C3SDA
I2C3
I2C3SCL

I2C2SDA
I2C2
I2C2SCL
SCI3 SPI2 SPI1 ECP GIO/EBM
I2C1SDA
I2C1
I2C1SCL
SPI2SIMO
SPI2SOMI

SPI1SIMO
SPI1SOMI
SPI2SCS

SPI2CLK

SPI1SCS

SPI1CLK
SCI3CLK

SPI2ENA

SPI1ENA
SCI3RX
SCI3TX

GIOA[1]/INT[1]/ECLK

GIOA[0]/INT[0]

GIOF[7:0]
GIOA[7:2]/INT[7:2]

GIOH[5,0]
GIOC[4:0]
GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOB[0]

GIOG[7:0]

A. The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.

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SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

Table 2. Terminal Functions

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
HIGH-END TIMER (HET)
HET[0] 73
HET[1] 72 Timer input capture or output compare. The
HET[2] 71 HET[8:0,18,20,22] applicable pins can be programmed
as general-purpose input/output (GIO) pins. All are
HET[3] 66
high-resolution pins.
HET[4] 65 The high-resolution (HR) SHARE feature allows even
HET[5] 63 HR pins to share the next higher odd HR pin
3.3 V 2 mA -z IPD (20 µA) structures. This HR sharing is independent of whether
HET[6] 9 or not the odd pin is available externally. If an odd pin
HET[7] 11 is available externally and shared, then the odd pin
can only be used as a general-purpose I/O. For more
HET[8] 12
information on HR SHARE, see the TMS470R1x
HET[18] 15 High-End Timer (HET) Reference Guide (literature
HET[20] 18 number SPNU199).

HET[22] 19
HIGH-END CAN CONTROLLER (HECC)
CAN1HRX 83 5-V tolerant 4 mA HECC1 receive pin or GIO pin
CAN1HTX 84 3.3 V 2 mA -z IPU (20 µA) HECC1 transmit pin or GIO pin
CAN2HRX 54 5-V tolerant 4 mA HECC2 receive pin or GIO pin
CAN2HTX 55 3.3 V 2 mA -z IPU (20 µA) HECC2 transmit pin or GIO pin
STANDARD CAN CONTROLLER (SCC)
SCC receive pin. The CANSRX signal is only
connected to the pad and not to a package pin. For
CANSRX - 5-V tolerant 4 mA
reduced power consumption in low power mode,
CANSRX should be driven output LOW.
SCC transmit pin. The CANSTX signal is only
connected to the pad and not to a package pin. For
CANSTX - 3.3 V 2 mA -z IPU (20 µA)
reduced power consumption in low power mode,
CANSTX should be driven output LOW.
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0] 141
GIOA[1]/INT[1]/ECLK 136
GIOA[2]/INT[2] 134 General-purpose input/output pins. GIOA[7:0]/INT[7:0]
GIOA[3]/INT[3] 133 are interrupt-capable pins.
5-V tolerant 4 mA GIOA[1]/INT[1]/ECLK pin is multiplexed with the
GIOA[4]/INT[4] 127 external clock-out function of the external clock
GIOA[5]/INT[5] 98 prescale (ECP) module.
GIOA[6]/INT[6] 78
GIOA[7]/INT[7] 79
GIOB[0]/EBDMAREQ0 43
GIOC[0]/EBOE 135
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOC[1]/EBWR[0] 128 GIOG[7:0], and GIOH[5,0] are multiplexed with the
3.3 V 2 mA -z IPD (20 µA) expansion bus module.
GIOC[2]/EBWR[1] 126
See Table 7.
GIOC[3]/EBCS[5] 120
GIOC[4]/EBCS[6] 119

(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2) All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)

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Table 2. Terminal Functions (continued)

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
GIOD[0]/EBADDR[0] 42
GIOD[1]/EBADDR[1] 39
GIOD[2]/EBADDR[2] 35
GIOD[3]/EBADDR[3] 30
GIOD[4]/EBADDR[4] 27
GIOD[5]/EBADDR[5] 23
GIOE[0]/EBDATA[0] 44
GIOE[1]/EBDATA[1] 47
GIOE[2]/EBDATA[2] 58
GIOE[3]/EBDATA[3] 61
GIOE[4]/EBDATA[4] 64
GIOE[5]/EBDATA[5] 67
GIOE[6]/EBDATA[6] 70
GIOE[7]/EBDATA[7] 77
GIOF[0]/INT[8]/
80
EBADDR[6]/EBDATA[8]
GIOF[1]/INT[9]/
82
EBADDR[7]/EBDATA[9]
GIOF[2]/INT[10]/
89
EBADDR[8]/EBDATA[10]
GIOF[3]/INT[11]/
90
EBADDR[9]/EBDATA[11] GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], and GIOH[5,0] are multiplexed with the
GIOF[4]/INT[12]/
93 3.3 V 2 mA -z IPD (20 µA) expansion bus module.
EBADDR[10]/EBDATA[12]
GIOF[7:0]/INT[15:8] are interrupt-capable pins.
GIOF[5]/INT[13]/
96 See Table 7.
EBADDR[11]/EBDATA[13]
GIOF[6]/INT[14]/
99
EBADDR[12]/EBDATA[14]
GIOF[7]/INT[15]/
100
EBADDR[13]/EBDATA[15]
GIOG[0]/EBADDR[14]/
20
EBADDR[6]
GIOG[1]/EBADDR[15]/
10
EBADDR[7]
GIOG[2]/EBADDR[16]/
8
EBADDR[8]
GIOG[3]/EBADDR[17]/
6
EBADDR[9]
GIOG[4]/EBADDR[18]/
3
EBADDR[10]
GIOG[5]/EBADDR[19]/
143
EBADDR[11]
GIOG[6]/EBADDR[20]/EB
142
ADDR[12]
GIOG[7]/EBADDR[21]/
140
EBADDR[13]
GIOH[0]/EBADDR[22]/
139
EBADDR[14]
GIOH[5]/EBHOLD 125

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Table 2. Terminal Functions (continued)

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
MibADC event input. Can be programmed as a GIO
ADEVT 101 2 mA -z IPD (20 µA)
pin.
ADIN[0] 117
ADIN[1] 116
ADIN[2] 115
ADIN[3] 114
ADIN[4] 113
3.3 V
ADIN[5] 108
MibADC analog input pins
ADIN[6] 107
ADIN[7] 106
ADIN[8] 105
ADIN[9] 104
ADIN[10] 103
ADIN[11] 102
ADREFHI 109 3.3 VREF MibADC module high-voltage reference input
ADREFLO 110 GND REF MibADC module low-voltage reference input
VCCAD 111 3.3-V PWR MibADC analog supply voltage
VSSAD 112 GND MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1 clock. SPI1CLK can be programmed as a GIO
SPI1CLK 4
pin.
SPI1ENA 2 SPI1 chip enable. Can be programmed as a GIO pin.
SPI1 slave chip select. Can be programmed as a GIO
SPI1SCS 1
5-V tolerant 4 mA pin.
SPI1 data stream. Slave in/master out. Can be
SPI1SIMO 5
programmed as a GIO pin.
SPI1 data stream. Slave out/master in. Can be
SPI1SOMI 7
programmed as a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK 56 SPI2 clock. Can be programmed as a GIO pin.
SPI2ENA 60 SPI2 chip enable. Can be programmed as a GIO pin.
SPI2 slave chip select. Can be programmed as a GIO
SPI2SCS 62
pin.
5-V tolerant 4 mA
SPI2 data stream. Slave in/master out. Can be
SPI2SIMO 59
programmed as a GIO pin.
SPI2 data stream. Slave out/master in. Can be
SPI2SOMI 57
programmed as a GIO pin.
INTER-INTEGRATED CIRCUIT 1 (I2C1)
I2C1SDA 87 I2C1 serial data pin or GIO pin
5-V tolerant 4 mA
I2C1SCL 88 I2C1 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 2 (I2C2)
I2C2SDA 94 I2C2 serial data pin or GIO pin
5-V tolerant 4 mA
I2C2SCL 95 I2C2 serial clock pin or GIO pin

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Table 2. Terminal Functions (continued)

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SDA 29 I2C3 serial data pin or GIO pin
5-V tolerant 4 mA
I2C3SCL 28 I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
I2C4SDA 41 I2C4 serial data pin or GIO pin
5-V tolerant 4 mA
I2C4SCL 40 I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
I2C5SDA 38 I2C5 serial data pin or GIO pin
5-V tolerant 4 mA
I2C5SCL 37 I2C5 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN 33 1.8 V Crystal connection pin or external clock input
OSCOUT 32 2 mA External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed
and the oscillator becomes the system clock. If not in
PLLDIS 97 3.3 V IPD (20 µA) bypass mode, TI recommends that this pin be
connected to ground or pulled down to ground by an
external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1 clock. SCI1CLK can be programmed as a GIO
SCI1CLK 48 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI1 data receive. SCI1RX can be programmed as a
SCI1RX 46 5-V tolerant 4 mA
GIO pin.
SCI1 data transmit. SCI1TX can be programmed as a
SCI1TX 45 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2 clock. SCI2CLK can be programmed as a GIO
SCI2CLK 51 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI2 data receive. SCI2RX can be programmed as a
SCI2RX 50 5-V tolerant 4 mA
GIO pin.
SCI2 data transmit. SCI2TX can be programmed as a
SCI2TX 49 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
SCI3 clock. SCI3CLK can be programmed as a GIO
SCI3CLK 24 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI3 data receive. SCI3RX can be programmed as a
SCI3RX 22 5-V tolerant 4 mA
GIO pin.
SCI3 data transmit. SCI3TX can be programmed as a
SCI3TX 21 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a
CLKOUT 81 3.3 V 8 mA
GIO pin or the output of SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External VCC
PORRST 118 3.3 V IPD (20 µA)
monitor circuitry must assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a
reset, and an external system reset can assert a
device reset.
On this pin, the output buffer is implemented as an
RST 121 3.3 V 4 mA IPU (20 µA)
open drain (drives low only).
To ensure an external reset is not arbitrarily generated,
TI recommends that an external pullup resistor be
connected to this pin.

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Table 2. Terminal Functions (continued)

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a
system reset if the WD KEY is not written in time by
the system, providing an external RC network circuit is
connected. If the user is not using AWD, TI
AWD 36 3.3 V 8 mA recommends that this pin be connected to ground or
pulled down to ground by an external resistor.
For more details on the external RC network circuit,
see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
TEST/DEBUG (T/D)
TCK 76 IPD (20 µA) Test clock. TCK controls the test hardware (JTAG).
3.3 V Test data in. TDI inputs serial data to the test
TDI 74 8 mA IPU (20 µA) instruction register, test data register, and
programmable test address (JTAG).
Test data out. TDO outputs serial data from the test
TDO 75 8 mA IPD (20 µA) instruction register, test data register, identification
register, and programmable test address (JTAG).
Test enable. Reserved for internal use only. TI
TEST 124 IPD (20 µA) recommends that this pin be connected to ground or
pulled down to ground by an external resistor.
Serial input for controlling the state of the CPU test
TMS 17 8 mA IPU (20 µA)
access port (TAP) controller (JTAG).
3.3 V Serial input for controlling the second TAP. TI
TMS2 16 8 mA IPU (20 µA) recommends that this pin be connected to VCCIO or
pulled up to VCCIO by an external resistor.
Test hardware reset to TAP1 and TAP2. IEEE
Standard 1149-1 (JTAG) Boundary-Scan Logic. TI
TRST 144 IPD (20 µA)
recommends that this pin be pulled down to ground by
an external resistor.
FLASH
Flash test pad 2. For proper operation, this pin must
FLTP2 132 NC NC
not be connected [no connect (NC)].
VCCP 131 3.3-V PWR Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
13
31
53
VCC 1.8-V PWR Core logic supply voltage
92
123
130
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
25
69
VCCIO 3.3-V PWR Digital I/O supply voltage
86
137

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Table 2. Terminal Functions (continued)

TERMINAL INTERNAL
CURRENT
TYPE (1) (2) PULLUP/ DESCRIPTION
NAME NO. OUTPUT
PULLDOWN (3)
SUPPLY GROUND CORE
14
34
52
VSS GND Core supply ground reference
91
122
129
SUPPLY GROUND DIGITAL I/O
26
68
VSSIO GND Digital I/O supply ground reference
85
138

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B1M Device-Specific Information

Memory
Figure 1 shows the memory map of the B1M device.
Memory (4G Bytes)
0xFFFF_FFFF 0xFFFF_FFFF
SYSTEM with PSA, CIM, RTI,
System Module Control
DEC, DMA, MMC, DWD
Registers
0xFFFF_FD00
(512K Bytes) IEM
0xFFF8_0000 0xFFFF_FC00
MSM
0xFFF7_FFFF 0xFFFF_F700
Reserved
Peripheral Control Registers 0xFFF8_0000
(512K Bytes)
Reserved
0xFFF0_0000
HET 0xFFF7_FC00
0xFFEF_FFFF
Reserved Reserved
0xFFE8_C000
SPI1 0xFFF7_F800
0xFFE8_BFFF
Flash Control Registers SCI3 0xFFF7_F600
0xFFE8_8000
SCI2 0xFFF7_F500
0xFFE8_7FFF
Reserved SCI1 0xFFF7_F400
0xFFE8_4021
Reserved
0xFFE8_4020
MPU Control Registers MibADC 0xFFF7_F000
0xFFE8_4000
ECP 0xFFF7_EF00
Reserved
Reserved (1 MByte) EBM 0xFFF7_ED00
GIO 0xFFF7_EC00
0xFFE0_0000
Reserved
HECC2 0xFFF7_EA00
Reserved
HECC1 0xFFF7_E800
0x7FFF_FFFF Reserved
HECC2 RAM 0xFFF7_E600
Reserved
HECC1 RAM 0xFFF7_E400
Reserved
SCC 0xFFF7_E000
RAM Reserved
(64K Bytes) SCC RAM 0xFFF7_DC00
I2C4 0xFFF7_DB00
Program I2C3 0xFFF7_DA00
and FLASH I2C2 0xFFF7_D900
Data Area (1M Bytes) I2C1 0xFFF7_D800
2 Banks
16 sectors I2C5 0xFFF7_D500
SPI2 0xFFF7_D400
Reserved 0xFFF0_0000
HET RAM
(1K Bytes) 0x0000_0023
Reserved
0x0000_0020
FIQ
0x0000_001C
IRQ
0x0000_0018
Reserved
0x0000_0024 0x0000_0014
Data Abort
0x0000_0023 0x0000_0010
Prefetch Abort
Exception, Interrupt, and 0x0000_000C
Software Interrupt
Reset Vectors 0x0000_0008
Undefined Instruction
0x0000_0004
0x0000_0000 Reset
0x0000_0000

A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not part of the memory map.

Figure 1. TMS470R1B1M Memory Map

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memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 3.

Table 3. TMS470R1B1M Memory Selection Assignment

MEMORY
MEMORY MEMORY MEMORY BASE ADDRESS STATIC MEM
SELECTED MPU MSM
SELECT SIZE (1) REGISTER CTL REGISTER
(ALL INTERNAL)
0 (fine) FLASH/ROM NO YES MFBAHR0 and MFBALR0
1M
1 (fine) FLASH/ROM NO YES MFBAHR1 and MFBALR1
2 (fine) RAM YES YES MFBAHR2 and MFBALR2
64 K (2)
3 (fine) RAM YES YES MFBAHR3 and MFBALR3
4 (fine) HET RAM 1K NO NO MFBAHR4 and MFBALR4 SMCR1
128 MB (x8)
5 (coarse) CS[5]/GIOC[3] NO NO MCBAHR2 and MCBALR2 SMCR5
512 K (x16)
128 MB (x8)
6 (coarse) CS[6]/GIOC[4] NO NO MCBAHR3 and MCBALR3 SMCR6
512 K (x16)

(1) x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
(2) The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.

JTAG security module

The B1M device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the
B1M, the visible unlock code is in the OTP sector at address 0x0000_01F8.

memory security module

The B1M device also includes a memory security module (MSM) to provide additional security and flexibility to
the memory contents' protection. The password for unlocking the MSM is located in the four words just before
the flash protection keys.

RAM
The B1M device contains 64K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This B1M RAM is implemented in one 64K-byte array
selected by two memory-select signals. This B1M configuration imposes an additional constraint on the memory
map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the
multiples of the size of the physical RAM (i.e., 64K bytes for the B1M device). The B1M RAM is addressed
through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).

F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the Flash read and Flash program and erase sections.

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flash protection keys

The B1M device provides flash protection keys. These four 32-bit protection keys prevent
program/erase/compaction operations from occurring until after the four protection keys have been matched by
the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B1M are
located in the last 4 words of the first 64K sector.

flash read
The B1M flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.

NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).

flash pipeline mode

When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system
clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).

NOTE:
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0).
In other words, the B1M device powers up and comes out of reset in non-pipeline
mode. Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will
override pipeline mode.

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flash program and erase

The B1M device flash contains two 512K-byte memory arrays (or banks), for a total of 1M-byte of flash, and
consists of sixteen sectors. These sixteen sectors are sized as follows:
SECTOR MEMORY ARRAYS
SEGMENT LOW ADDRESS HIGH ADDRESS
NO. (OR BANKS)
OTP 2K Bytes 0x0000_0000 0x0000_007FF
0 64K Bytes 0x0000_0000 0x0000_FFFF
1 64K Bytes 0x0001_0000 0x0001_FFFF
2 64K Bytes 0x0002_0000 0x0002_FFFF
BANK0
3 64K Bytes 0x0003_0000 0x0003_FFFF
(512K Bytes)
4 64K Bytes 0x0004_0000 0x0004_FFFF
5 64K Bytes 0x0005_0000 0x0005_FFFF
6 64K Bytes 0x0006_0000 0x0006_FFFF
7 64K Bytes 0x0007_0000 0x0007_FFFF

0 64K Bytes 0x0008_0000 0x0008_FFFF

1 64K Bytes 0x0009_0000 0x0009_FFFF
2 64K Bytes 0x000A_0000 0x000A_FFFF
3 64K Bytes 0x000B_0000 0x000B_FFFF BANK1
4 64K Bytes 0x000C_0000 0x000C_FFFF (512K Bytes)
5 64K Bytes 0x000D_0000 0x000D_FFFF
6 64K Bytes 0x000E_0000 0x000E_FFFF
7 64K Bytes 0x000F_0000 0x000F_FFFF

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.

NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.

NOTE:
When the OTP sector is enabled, the rest of flash memory is disabled. The OTP
memory can only be read or programmed from code executed out of RAM.

HET RAM
The B1M device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.

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peripheral selects and base addresses

The B1M device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the
SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.

Table 4. B1M Peripherals, System Module, and Flash Base Addresses

ADDRESS RANGE
CONNECTING MODULE PERIPHERAL SELECTS
BASE ADDRESS ENDING ADDRESS
SYSTEM 0 x FFFF_FFCC 0 x FFFF_FFFF N/A
RESERVED 0 x FFFF_FF70 0 x FFFF_FFCB N/A
DWD 0xFFFF_FF60 0 x FFFF_FF6F N/A
PSA 0 x FFFF_FF40 0 x FFFF_FF5F N/A
CIM 0 x FFFF_FF20 0 x FFFF_FF3F N/A
RTI 0 x FFFF_FF00 0 x FFFF_FF1F N/A
DMA 0 x FFFF_FE80 0 x FFFF_FEFF N/A
DEC 0 x FFFF_FE00 0 x FFFF_FE7F N/A
RESERVED 0xFFFF_FD80 0xFFFF_FDFF N/A
MMC 0 x FFFF_FD00 0 x FFFF_FD7F N/A
IEM 0 x FFFF_FC00 0 x FFFF_FCFF N/A
RESERVED 0 x FFFF_Fb00 0 x FFFF_FBFF N/A
RESERVED 0 x FFFF_Fa00 0 x FFFF_FAFF N/A
DMA CMD BUFFER 0 x FFFF_F800 0 x FFFF_F9FF N/A
MSM 0xFFFF_F700 0xFFFF_F7FF N/A
RESERVED 0xFFF8_0000 0xFFFF_F6FF N/A
RESERVED 0 x FFF7_FD00 0xFFF7_FFFF
PS[0]
HET 0xFFF7_FC00 0xFFF7_FCFF
RESERVED 0xFFF7_F900 0xFFF7_FBFF
PS[1]
SPI1 0xFFF7_F800 0xFFF7_F8FF
RESERVED 0xFFF7_F700 0xFFF7_F7FF
SCI3 0xFFF7_F600 0xFFF7_F6FF
PS[2]
SCI2 0XFFF7_F500 0XFFF7_F5FF
SCI1 0xFFF7_F400 0xFFF7_F4FF
RESERVED 0xFFF7_F100 0xFFF7_F3FF
PS[3]
MibADC 0xFFF7_F000 0xFFF7_F0FF
ECP 0xFFF7_EF00 0xFFF7_EFFF
RESERVED 0xFFF7_EE00 0xFFF7_EEFF
PS[4]
EBM 0xFFF7_ED00 0xFFF7_EDFF
GIO 0xFFF7_EC00 0xFFF7_ECFF
0xFFF7_EB00 0xFFF7_EBFF
HECC2
0xFFF7_EA00 0xFFF7_EAFF
PS[5]
0xFFF7_E900 0xFFF7_E9FF
HECC1
0xFFF7_E800 0xFFF7_E8FF
0xFFF7_E700 0xFFF7_E7FF
HECC2 RAM
0xFFF7_E600 0xFFF7_E6FF
PS[6]
0xFFF7_E500 0xFFF7_E5FF
HECC1 RAM
0xFFF7_E400 0xFFF7_E4FF
RESERVED 0xFFF7_E100 0xFFF7_E3FF
PS[7]
SCC 0xFFF7_E000 0xFFF7_E0FF

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Table 4. B1M Peripherals, System Module, and Flash Base Addresses (continued)
ADDRESS RANGE
CONNECTING MODULE PERIPHERAL SELECTS
BASE ADDRESS ENDING ADDRESS
RESERVED 0xFFF7_DD00 0xFFF7_DFFF
PS[8]
SCC RAM 0xFFF7_DC00 0xFFF7_DCFF
I2C4 0xFFF7_DB00 0xFFF7_DBFF
I2C3 0xFFF7_DA00 0xFFF7_DAFF
PS[9]
I2C2 0xFFF7_D900 0xFFF7_D9FF
I2C1 0xFFF7_D800 0xFFF7_D8FF
RESERVED 0xFFF7_D600 0xFFF7_D7FF
I2C5 0xFFF7_D500 0xFFF7_D5FF PS[10]
SPI2 0xFFF7_D400 0xFFF7_D4FF
RESERVED 0xFFF7_CC00 0xFFF7_D3FF PS[11] – PS[12]
RESERVED 0xFFF7_C800 0xFFF7_CBFF PS[13]
RESERVED 0xFFF7_C000 0xFFF7_C7FF PS[14] – PS[15]
RESERVED 0xFFF0_0000 0xFFF7_BFFF N/A
FLASH CONTROL REGISTERS 0xFFE8_8000 0xFFE8_BFFF N/A
RESERVED 0xFFF8_4024 0xFFF8_7FFF N/A
MPU CONTROL REGISTERS 0xFFE8_4000 0xFFE8_4023 N/A
RESERVED 0xFFF8_0000 0xFFF8_3FFF N/A

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direct-memory access (DMA)

The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA
controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in parallel
with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the B1M device, the DMA controller
configuration is 32 control packets and 16 channels.
For the B1M DMA request hardwired configuration, see Table 5.

Table 5. DMA Request Lines Connections (1)

MODULES DMA REQUEST INTERRUPT SOURCES DMA CHANNEL
EBM Expansion Bus DMA request EBDMAREQ[0] DMAREQ[0]
SPI1/I2C4 SPI1 end-receive/I2C4 read SPI1DMA0/I2C4DMA0 DMAREQ[1]
SPI1/I2C4 SPI1 end-transmit/I2C4 write SPI1DMA1/I2C4DMA1 DMAREQ[2]
MibADC/I2C1 ADC EV/I2C1 read MibADCDMA0/I2C1DMA0 DMAREQ[3]
MibADC/SCI1/I2C5 ADC G1/SCI1 end-receive/I2C5 read MibADCDMA1/SCI1DMA0/I2C5DMA0 DMAREQ[4]
MibADC/SCI1/I2C5 ADC G2/SCI1 end-transmit/I2C5 write MibADCDMA2/SCI1DMA1/I2C5DMA1 DMAREQ[5]
I2C1 I2C1 write I2C1DMA1 DMAREQ[6]
SCI3/SPI2 SCI3 end-receive/SPI2 end-receive SCI3DMA0/SPI2DMA0 DMAREQ[7]
SCI3/SPI2 SCI3 end-transmit/SPI2 end-transmit SCI3DMA01SPI2DMA1 DMAREQ[8]
I2C2 I2C2 read end-receive I2C2DMA0 DMAREQ[9]
I2C2 I2C2 write end-transmit I2C2DMA1 DMAREQ[10]
I2C3 I2C3 read I2C3DMA0 DMAREQ[11]
I2C3 I2C3 write I2C3DMA1 DMAREQ[12]
Reserved DMAREQ[13]
SCI2 SCI2 end-receive SCI2DMA0 DMAREQ[14]
SCI2 SCI2 end-transmit SCI2DMA1 DMAREQ[15]

(1) For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a
given application. The device has software control to ensure that there are no conflicts between requesting modules.

Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
• Non-request mode (used when transferring from memory to memory)
• Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).

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interrupt priority (IEM to CIM)

Interrupt requests originating from the B1M peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.) are
assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register
mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS
module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order in
the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 6.

Table 6. Interrupt Priority (IEM and CIM)

DEFAULT CIM INTERRUPT
MODULES INTERRUPT SOURCES IEM CHANNEL
LEVEL/CHANNEL
SPI1 SPI1 end-transfer/overrun 0 0
RTI COMP2 interrupt 1 1
RTI COMP1 interrupt 2 2
RTI TAP interrupt 3 3
SPI2 SPI2 end-transfer/overrun 4 4
GIO GIO interrupt A 5 5
Reserved 6 6
HET HET interrupt 1 7 7
I2C1 I2C1 interrupt 8 8
SCI1/SCI2 SCI1 or SCI2 error interrupt 9 9
SCI1 SCI1 receive interrupt 10 10
Reserved 11 11
I2C2 I2C2 interrupt 12 12
HECC1 HECC1 interrupt A 13 13
SCC SCC interrupt A 14 14
Reserved 15 15
MibADC MibADC end event conversion 16 16
SCI2 SCI2 receive interrupt 17 17
DMA DMA interrupt 0 18 18
I2C3 I2C3 interrupt 19 19
SCI1 SCI1 transmit interrupt 20 20
System SW interrupt (SSI) 21 21
Reserved 22 22
HET HET interrupt 2 23 23
HECC1 HECC1 interrupt B 24 24
SCC SCC interrupt B 25 25
SCI2 SCI2 transmit interrupt 26 26
MibADC MibADC end Group 1 conversion 27 27
DMA DMA Interrupt 1 28 28
GIO GIO interrupt B 29 29
MibADC MibADC end Group 2 conversion 30 30
SCI3 SCI3 error interrupt 31 31

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Table 6. Interrupt Priority (IEM and CIM) (continued)

DEFAULT CIM INTERRUPT
MODULES INTERRUPT SOURCES IEM CHANNEL
LEVEL/CHANNEL
Reserved 31 32–37
HECC2 HECC2 interrupt A 31 38
HECC2 HECC2 interrupt B 31 39
SCI3 SCI3 receive interrupt 31 40
SCI3 SCI3 transmit interrupt 31 41
I2C4 I2C4 interrupt 31 42
I2C5 I2C5 interrupt 31 43
Reserved 31 44–47

For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).

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expansion bus module (EBM)

The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output
pins and expansion bus interface pins. This module supports the multiplexing of the GIO and the expansion bus
interface functions. The module also supports 8- and 16- bit expansion bus memory interface mappings as well
as mapping of the following expansion bus signals:
• 27-bit address bus (EBADDR[26:0] for x8, 19-bit address bus (EBADDR[18:0] for x16
• 8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
• 2 write strobes (EBWR[1:0])
• 2 memory chip selects (EBCS[6:5])
• 1 output enable (EBOE)
• 1 external hold signal for interfacing to slow memories (EBHOLD)
• 1 DMA request line (EBDMAREQ[0])
Table 7 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these
pins varies depending on the memory mode.

Table 7. Expansion Bus Mux Mapping (1)

EXPANSION BUS MODULE PINS
GIO
x8 (2) x16 (2)
GIOB[0] EBDMAREQ[0] EBDMAREQ[0]
GIOC[0] EBOE EBOE
GIOC[2:1] EBWR[1:0] EBWR[1:0]
GIOC[4:3] EBCS[6:5] EBCS[6:5]
GIOD[5:0] EBADDR[5:0] EBADDR[5:0]
GIOE[7:0] EBDATA[7:0] EBDATA[7:0]
GIOF[7:0] EBADDR[13:6] EBDATA[15:8]
GIOG[7:0] EBADDR[21:14] EBADDR[13:6]
GIOH[5] EBHOLD EBHOLD
I2C5SDA EBADDR[26] EBADDR[18]
I2C5SCL EBADDR[25] EBADDR[17]
I2C4SCL EBADDR[24] EBADDR[16]
I2C4SDA EBADDR[23] EBADDR[15]
GIOH[0] EBADDR[22] EBADDR[14]

(1) For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222) and
the TMS470R1x General Purpose Input/Output Reference Guide (literature number SPNU192).
(2) X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.

Table 8 lists the names of the expansion bus interface signals and their functions.

Table 8. Expansion Bus Pins

PIN DESCRIPTION
EBDMAREQ Expansion bus DMA request
EBOE Expansion bus pin enable
EBWR Expansion bus write strobe EBWR[1] controls EBDATA[15:8] and EBWR[0]
controls EBDATA[7:0]
EBCS Expansion bus chip select
EBADDR Expansion bus address pins
EBDATA Expansion bus data pins
EBHOLD Expansion bus hold: An external device may assert this signal to add wait
states to an expansion bus transaction.

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MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The B1M MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts or by the DMA.

MibADC event trigger enhancements

The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
• Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
• The trigger source and polarity can be selected individually for both group1 and the event group from the
options identified in Table 9.

Table 9. MibADC Event Hookup Configuration

SOURCE SELECT BITS FOR G1 OR EVENT
EVENT # SIGNAL PIN NAME
(G1SRC[1:0] OR EVSRC[1:0])
EVENT1 00 ADEVT
EVENT2 01 HET18
EVENT3 10 Reserved
EVENT4 11 Reserved

For group1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in
the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).

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JTAG Interface
There are two main test access ports (TAPs) on the device:
• TMS470R1x CPU TAP
• Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 2.
TMS470R1x CPU

TCK TCK
TRST TRST
TMS TMS
TDI TDI TDO TDO

Factory Test

TCK
TRST
TMS2 TMS
TDI TDO

Figure 2. JTAG Interface

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documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of
documentation available include data sheets with design specifications; complete user's guides for all devices
and development support tools; and hardware and software applications. Useful reference documentation
includes:
• Bulletin
– TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)
• User's Guides
– TMS470R1x System Module Reference Guide (literature number SPNU189)
– TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
– TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
– TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
– TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)
– TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
– TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)
– TMS470R1x Zero Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number
SPNU212)
– TMS470R1x Digital Watchdog Timer Reference Guide (literature number SPNU244)
– TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211)
– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
– TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222)
– TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
– TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245)
– TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246)
– TMS470 Peripherals Overview Reference Guide (literature number SPNU248)
• Errata Sheet
– TMS470R1B1M TMS470 Microcontrollers Silicon Errata (literature number SPNZ139)

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Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS470R1B1M). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Figure 3 illustrates the numbering and symbol nomenclature for the TMS470R1x family.

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TMS 470 R1 B 1M PGE A

PREFIX OPTIONS
TMS = Fully Qualified Device

FAMILY TEMPERATURE RANGE

470 = TMS470 RISC − Embedded A = −40°C − 85 °C
Microcontroller Family
PACKAGE TYPE
ARCHITECTURE PGE = 144-pin Low-Profile Quad Flatpack (LQFP)
R1 = ARM7TDM1 CPU
REVISION CHANGE
DEVICE TYPE B Blank = Original
With 1024K−Bytes Flash Memory:
60−MHZ Frequency FLASH MEMORY
1.8-V Core, 3.3-V I/O 1M = 1024K−Bytes Flash Memory
Flash Program Memory
ZPLL Clock
64K−Byte Static RAM
1K−Byte HET RAM (64 Instructions)
AWD
DWD
RTI
10−Bit, 12−Input MibADC
Two SPI Modules
Three SCI Modules
Two High−End CAN HECC
HET, 16 Channels
ECP
IEM
DMA
Five I2C Modules
EMB
MSM

Figure 3. TMS470R1x Family Nomenclature

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device identification code register

The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 10). The B1M device identification code register
value is 0xnA5F.
Figure 4. TMS470 Device ID Bit Allocation Register [offset = 0xFFFF_FFF0h]
31 16

Reserved

15 12 11 10 9 3 2 1 0

VERSION TF R/F PART NUMBER 1 1 1

R-K R-K R-K R-K R-1 R-1 R-1
LEGEND:
For bits 3-15: R = Read only, -K = Value constant after RESET.
For bits 0-2: R = Read only, -1 = Value after RESET.
Table 10. TMS470 Device ID Bit Allocation Register Field Descriptions
Bit Field Value Description
31-16 Reserved Reads are undefined and writes have no effect.
15-12 VERSION Silicon version (revision) bits
These bits identify the silicon version of the device.
11 TF Technology family bit
This bit distinguishes the technology family core power supply:
0 3.3 V for F10/C10 devices
1 1.8 V for F05/C05 devices
10 R/F ROM/flash bit
This bit distinguishes between ROM and flash devices:
0 Flash device
1 ROM device
9-3 PART NUMBER Device-specific part number bits
These bits identify the assigned device-specific part number. The assigned device-specific part
number for the B1M device is 1001011.
2-0 1 Mandatory High
Bits 2, 1, and 0 are tied high by default.

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DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS

Absolute Maximum Ratings

over operating free-air temperature range, A version (unless otherwise noted) (1)

Supply voltage range: VCC (2) –0.3 V to 2.5 V

(2)
Supply voltage range: VCCIO, VCCAD, VCCP (flash pump) –0.3 V to 4.1 V
Input voltage range: All 5 V tolerant input pins – 0.3 V to 6.0 V
All other input pins –0.3 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST , TEST,
and TCK ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11] ±10 mA
Operating free-air temperature A version –40°C to 85°C
range, TA:
Operating junction temperature range, TJ: –40°C to 150°C
Storage temperature range, Tstg: –40°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated grounds.

Device Recommended Operating Conditions (1)

MIN NOM MAX UNIT
SYSCLK = 48 MHz
1.71 2.05
(pipeline mode enabled)
VCC Digital logic supply voltage (Core) V
SYSCLK = 60 MHz
1.81 2.05
(pipeline mode enabled)
VCCIO Digital logic supply voltage (I/O) 3 3.6 V
VCCAD ADC supply voltage 3 3.6 V
VCCP Flash pump supply voltage 3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD ADC supply ground (1) –0.1 0.1 V
TA Operating free-air temperature A version –40 85 °C
TJ Operating junction temperature –40 150 °C

(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.

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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (1)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
Vhys Input hysteresis 0.15 V
Low-level input
VIL All inputs (3) –0 .3 0.8 V
voltage
High-level input
VIH All inputs 2 VCCIO + 0. 3 V
voltage
Input threshold
VIH AWD only (4) 1.35 1.8 V
voltage
IOL = IOL MAX 0.2 VCCIO
VOL Low-level output voltage (5) V
IOL = 50 µA 0.2
IOH = IOH MIN 0.8 VCCIO
VOH High-level output voltage (5) V
IOH = 50 µA VCCIO – 0.2
VI < VSSIO – 0. 3 or VI > VCCIO +
IIC Input clamp current (I/O pins) (6) –2 2 mA
0. 3
IIL Pulldown VI = VSS –1 1
IIH Pulldown VI = VCCIO 5 40
Input current
IIL Pullup VI = VSS –40 –5 µA
(3.3 V input pins)
IIH Pullup VI = VCCIO –1 1
II All other pins No pullup or pulldown –1 1
VI = VSS –1 1
VI = VCCIO 1 5
Input current (5 V tolerant input pins) µA
VI = 5 V 5 25
VI = 5.5 V 25 50
CLKOUT, AWD, TDI,
8
TDO, TMS, TMS2
Low-level output RST 4
IOL VOL = VOL MAX mA
current
All other 3.3 V I/O (7) 2
5 V tolerant 4
CLKOUT, TDI, TDO,
–8
TMS, TMS2
High-level output RST –4
IOH VOH = VOH MIN mA
current
All other 3.3 V I/O (7) –2
5 V tolerant –4
SYSCLK = 48 MHz,
110 mA
ICLK = 24 MHz, VCC = 2.05 V
VCC Digital supply current (operating mode)
SYSCLK = 60 MHz,
ICC 125 mA
ICLK = 30 MHz, VCC = 2.05 V
VCC Digital supply current (standby mode) (8) (9) OSCIN = 5 MHz, VCC = 2.05 V 1.30 mA
VCC Digital supply current (halt mode) (8) (9) All frequencies, VCC = 2.05 V 700 µA

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal VCC,
VCCIO, or VCCAD, room temperature.
(3) This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST Timings section.
(4) These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
(5) VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
(6) Parameter does not apply to input-only or output-only pins.
(7) Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal
Functions table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the
resulting value will always be low.
(8) For flash banks/pumps in sleep mode.
(9) For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
VCCIO Digital supply current (operating mode) No DC load, VCCIO = 3.6 V (10) 15 mA
ICCIO VCCIO Digital supply current (standby mode) (9) No DC load, VCCIO = 3.6 V (10) 10 µA
VCCIO Digital supply current (halt mode) (9) No DC load, VCCIO = 3.6 V (10) 10 µA
VCCAD supply current (operating mode) All frequencies, VCCAD = 3.6 V 15 mA
ICCAD VCCAD supply current (standby mode) All frequencies, VCCAD = 3.6 V 10 µA
VCCAD supply current (halt mode) All frequencies, VCCAD = 3.6 V 10 µA
SYSCLK = 48 MHz, VCCP = 3.6 V
45 mA
read operation
SYSCLK = 60 MHz, VCCP = 3.6 V
55 mA
read operation
ICCP VCCP pump supply current VCCP = 3.6 V program and erase 70 mA
VCCP = 3.6 V standby mode
10 µA
operation (8)
VCCP = 3.6 V halt mode
10 µA
operation (8)
CI Input capacitance 2 pF
CO Output capacitance 3 pF

(10) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO – 0.2 V.

Parameter Measurement Information

IOL

Tester Pin
Electronics

50 Ω Output
V LOAD Under
Test
CL

I OH

Where: IOL = IOL MAX for the respective pin (A)

IOH = IOH MIN for the respective pin(A)
VLOAD = 1.5 V
CL = 150-pF typical load-circuit capacitance(B)

A. For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"
table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.

Figure 5. Test Load Circuit

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Timing Parameter Symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:

CM Compaction, CMPCT RD Read

CO CLKOUT RST Reset, RST
ER Erase RX SCInRX
ICLK Interface clock S Slave mode
M Master mode SCC SCInCLK
OSC, OSCI OSCIN SIMO SPInSIMO
OSCO OSCOUT SOMI SPInSOMI
P Program, PROG SPC SPInCLK
R Ready SYS System clock
R0 Read margin 0, RDMRGN0 TX SCInTX
R1 Read margin 1, RDMRGN1

Lowercase subscripts and their meanings are:

a access time r rise time

c cycle time (period) su setup time
d delay time t transition time
f fall time v valid time
h hold time w pulse duration (width)

The following additional letters are used with these meanings:

H High X Unknown, changing, or don't care level

L Low Z High impedance
V Valid

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External Reference Resonator/Crystal Oscillator Clock Option

The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6a. The oscillator is a single-stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement
and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 6b.

OSCIN OSCOUT OSCIN OSCOUT

C1(A) Crystal C2(A) External

Clock Signal
(toggling 0-1.8 V)

(a) (b)
A. The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 6. Crystal/Clock Connection

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ZPLL AND CLOCK SPECIFICATIONS

Timing Requirements for ZPLL Circuits Enabled or Disabled

MIN TYP MAX UNIT
f(OSC) Input clock frequency 4 10 MHz
tc(OSC) Cycle time, OSCIN 100 ns
tw(OSCIL) Pulse duration, OSCIN low 15 ns
tw(OSCIH) Pulse duration, OSCIN high 15 ns
f(OSCRST) OSC FAIL frequency (1) 53 kHz

(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).

Switching Characteristics over Recommended Operating Conditions for Clocks (1) (2) (3)
PARAMETER TEST CONDITIONS (4) MIN MAX UNIT
Pipeline mode enabled 60 (6) MHz
f(SYS) System clock frequency (5)
Pipeline mode disabled 24 MHz
f(CONFIG) System clock frequency - flash config mode 24 MHz
Pipeline mode enabled 30 MHz
f(ICLK) Interface clock frequency
Pipeline mode disabled 24 MHz
Pipeline mode enabled 30 MHz
f(ECLK) External clock output frequency for ECP module
Pipeline mode disabled 24 MHz
Pipeline mode enabled 16.7 ns
tc(SYS) Cycle time, system clock
Pipeline mode disabled 41.6 ns
tc(CONFIG) Cycle time, system clock - flash config mode 41.6 ns
Pipeline mode enabled 33.3 ns
tc(ICLK) Cycle time, interface clock
Pipeline mode disabled 41.6 ns
Pipeline mode enabled 33.3 ns
tc(ECLK) Cycle time, ECP module external clock output
Pipeline mode disabled 41.6 ns

(1) f(SYS) = M × f(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f(SYS) = f(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2) f(ECLK) = f(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) Only ZPLL mode is available. FM mode must not be turned on.
(4) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(5) Flash Vread must be set to 5 V to achieve maximum system clock frequency.
(6) Operating VCC range for this system clock frequency is 1.81 to 2.05 V.

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Switching Characteristics over Recommended Operating Conditions for External Clocks (1) (2) (3)
(see Figure 7 and Figure 8)
PARAMETER TEST CONDITIONS MIN MAX UNIT
SYSCLK or MCLK (4) 0.5tc(SYS) – tf
tw(COL) Pulse duration, CLKOUT low ICLK: X is even or 1 (5) 0.5tc(ICLK) – tf ns
ICLK: X is odd and not 1 (5) 0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK (4) 0.5tc(SYS) – tr
tw(COH) Pulse duration, CLKOUT high ICLK: X is even or 1 (5) 0.5tc(ICLK) – tr ns
ICLK: X is odd and not 1 (5) 0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd 0.5tc(ECLK) – tf
tw(EOL) Pulse duration, ECLK low N is odd and X is even 0.5tc(ECLK) – tf ns
N is odd and X is odd and not 1 0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd 0.5tc(ECLK) – tr
tw(EOH) Pulse duration, ECLK high N is odd and X is even 0.5tc(ECLK) – tr ns
N is odd and X is odd and not 1 0.5tc(ECLK) – 0.5tc(SYS) – tr

(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
(2) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
(4) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
(5) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).

tw(COH)

CLKOUT

tw(COL)

Figure 7. CLKOUT Timing Diagram

tw(EOH)

ECLK

tw(EOL)

Figure 8. ECLK Timing Diagram

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RST AND PORRST TIMINGS

Timing Requirements for PORRST

(see Figure 9)
MIN MAX UNIT
VCCPORL VCC low supply level when PORRST must be active during power up 0.6 V
VCC high supply level when PORRST must remain active during power up and become
VCCPORH 1.5 V
active during power down
VCCIOPORL VCCIO low supply level when PORRST must be active during power up 1.1 V
VCCIO high supply level when PORRST must remain active during power up and become
VCCIOPORH 2.75 V
active during power down
VIL Low-level input voltage after VCCIO > VCCIOPORH 0.2 VCCIO V
VIL(PORRST) Low-level input voltage of PORRST before VCCIO > VCCIOPORL 0.5 V
tsu(PORRST)r Setup time, PORRST active before VCCIO > VCCIOPORL during power up 0 ms
tsu(VCCIO)r Setup time, VCCIO >VCCIOPORL before VCC > VCCPORL 0 ms
th(PORRST)r Hold time, PORRST active after VCC > VCCPORH 1 ms
tsu(PORRST)f Setup time, PORRST active before VCC ≤ VCCPORH during power down 8 µs
th(PORRST)rio Hold time, PORRST active after VCC > VCCIOPORH 1 ms
th(PORRST)d Hold time, PORRST active after VCC < VCCPORL 0 ms
tsu(PORRST)fio Setup time, PORRST active before VCC ≤ VCCIOPORH during power down 0 ns
tsu(VCCIO)f Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL 0 ns

V CCP /VCCIO
V CCIOPORH V CCIO V CCIOPORH
th(PORRST)rio
tsu(VCCIO)f

V CC
V CCPORH V CC V CCPORH
tsu(PORRST)f
th(PORRST)r tsu(PORRST)fio
V CCIOPORL tsu(PORRST)f V CCIOPORL
V CCPORL V CCPORL
th(PORRST)r
V CC tsu(VCCIO)r
VCCP/VCCIO tsu(PORRST)r th(PORRST)d

PORRST V IL(PORRST) V IL VIL VIL V IL V IL(PORRST)

NOTE: VCCIO > 1.1 V before VCC > 0.6 V

Figure 9. PORRST Timing Diagram

Switching Characteristics over Recommended Operating Conditions for RST (1)

PARAMETER MIN MAX UNIT
Valid time, RST active after PORRST inactive 4112tc(OSC)
tv(RST) ns
Valid time, RST active (all others) 8tc(SYS)
Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump
tfsu 836tc(OSC) ns
stabilization time)

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.

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JTAG SCAN INTERFACE TIMING (JTAG CLOCK SPECIFICATION 10-MHz AND 50-pF LOAD ON
TDO OUTPUT)
MIN MAX UNIT
tc(JTAG) Cycle time, JTAG low and high period 50 ns
tsu(TDI/TMS - TCKr) Setup time, TDI, TMS before TCK rise (TCKr) 15 ns
th(TCKr -TDI/TMS) Hold time, TDI, TMS after TCKr 15 ns
th(TCKf -TDO) Hold time, TDO after TCKf 10 ns
td(TCKf -TDO) Delay time, TDO valid after TCK fall (TCKf) 45 ns



 
 

 

     
     



    
    

Figure 10. JTAG Scan Timings

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OUTPUT TIMINGS

Switching Characteristics for Output Timings versus Load Capacitance ©L)

(see Figure 11)
PARAMETER MIN MAX UNIT
CL = 15 pF 0.5 2.5
CL = 50 pF 1.5 5.0
tr Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 ns
CL = 100 pF 3.0 9.0
CL = 150 pF 4.5 12.5
CL = 15 pF 0.5 2.5
CL = 50 pF 1.5 5.0
tf Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 ns
CL = 100 pF 3.0 9.0
CL = 150 pF 4.5 12.5
CL = 15 pF 2.5 8
CL = 50 pF 5 14
tr Rise time, RST ns
CL = 100 pF 9 23
CL = 150 pF 13 32
CL = 15 pF 3 10
CL = 50 pF 3.5 12
tr Rise time, 4mA, 5 V tolerant pins CL = 100 pF 7 21 ns
CL = 150 pF 9 28
CL = 400 pF 18 40
CL = 15 pF 2 8
CL = 50 pF 2.5 9
tf Fall time, 4mA, 5 V tolerant pins CL = 100 pF 8 25 ns
CL = 150 pF 11 35
CL = 400 pF 20 45
CL = 15 pF 2.5 10
CL = 50 pF 6.0 25
tr Rise time, all other output pins ns
CL = 100 pF 12 45
CL = 150 pF 18 65
CL = 15 pF 3 10
CL = 50 pF 8.5 25
tf Fall time, all other output pins ns
CL = 100 pF 16 45
CL = 150 pF 23 65

tr tf
VCC
Output 80% 80%

20% 20%
0

Figure 11. CMOS-Level Outputs

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INPUT TIMINGS

Timing Requirements for Input Timings (1)

(see Figure 12)
MIN MAX UNIT
tpw Input minimum pulse width tc(ICLK) + 10 ns

(1) tc(ICLK) = interface clock cycle time = 1/f(ICLK)

tpw
V CC
Input 80% 80%

20% 20%
0

Figure 12. CMOS-Level Inputs

FLASH TIMINGS

Timing Requirements for Program Flash (1)

MIN TYP MAX UNIT
tprog(16-bit) Half word (16-bit) programming time 4 16 200 µs
tprog(Total) 1M-byte programming time (2) 8 32 s
terase(sector) Sector erase time 1.7 s
twec Write/erase cycles at TA = –40°C to 85°C 50000 cycles
tfp(RST) Flash pump settling time from RST to SLEEP 167tc(SYS) ns
tfp(SLEEP) Initial flash pump settling time from SLEEP to STANDBY 167tc(SYS) ns
tfp(STANDBY) Initial flash pump settling time from STANDBY to ACTIVE 84tc(SYS) ns

(1) For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
(2) The 1M-byte programming time includes overhead of state machine.

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SPIn MASTER MODE TIMING PARAMETERS

SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 13)
NO. MIN MAX UNIT
1 tc(SPC)M Cycle time, SPInCLK (4) 100 256tc(ICLK)
tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)M – tr 0.5tc(SPC)M + 5
2 (5)
tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)M – tf 0.5tc(SPC)M + 5
tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)M – tf 0.5tc(SPC)M + 5
3 (5)
tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)M – tr 0.5tc(SPC)M + 5
td(SPCH-SIMO)M Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0) 10
4 (5)
td(SPCL-SIMO)M Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1) 10 ns
tv(SPCL-SIMO)M Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) tc(SPC)M – 5 – tf
5 (5)
tv(SPCH-SIMO)M Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M Setup time, SPInSOMI before SPInCLK low (clock polarity = 0) 6
6 (5)
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 1) 6
tv(SPCL-SOMI)M Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0) 4
7 (5)
tv(SPCH-SOMI)M Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1) 4

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

SPInCLK
(clock polarity = 0)

SPInCLK
(clock polarity = 1)

4
5

SPInSIMO Master Out Data Is Valid

Master In Data
SPInSOMI
Must Be Valid

Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 0)

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SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 14)
NO. MIN MAX UNIT
1 tc(SPC)M Cycle time, SPInCLK (4) 100 256tc(ICLK)
tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)M – tr 0.5tc(SPC)M + 5
2 (5)
tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)M – tf 0.5tc(SPC)M + 5
tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)M – tf 0.5tc(SPC)M + 5
3 (5)
tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)M – tr 0.5tc(SPC)M + 5
Valid time, SPInCLK high after SPInSIMO data valid
tv(SIMO-SPCH)M 0.5tc(SPC)M – 10
(clock polarity = 0)
4 (5)
Valid time, SPInCLK low after SPInSIMO data valid
tv(SIMO-SPCL)M 0.5tc(SPC)M – 10
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
tv(SPCH-SIMO)M 0.5tc(SPC)M – 5 – tr ns
(clock polarity = 0)
5 (5)
Valid time, SPInSIMO data valid after SPInCLK low
tv(SPCL-SIMO)M 0.5tc(SPC)M – 5 – tf
(clock polarity = 1)
Setup time, SPInSOMI before SPInCLK high
tsu(SOMI-SPCH)M 6
(clock polarity = 0)
6 (5)
Setup time, SPInSOMI before SPInCLK low
tsu(SOMI-SPCL)M 6
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
tv(SPCH-SOMI)M 4
(clock polarity = 0)
7 (5)
Valid time, SPInSOMI data valid after SPInCLK low
tv(SPCL-SOMI)M 4
(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2) tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

SPInCLK
(clock polarity = 0)

SPInCLK
(clock polarity = 1)

SPInSIMO Master Out Data Is Valid Data Valid

SPInSOMI Master In Data

Must Be Valid

Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)

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SPIn SLAVE MODE TIMING PARAMETERS

SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 15)
NO. MIN MAX UNI
T
1 tc(SPC)S Cycle time, SPInCLK (5) 100 256tc(ICLK)
tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
2 (6)
tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
3 (6)
tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
Delay time, SPInCLK high to SPInSOMI valid
td(SPCH-SOMI)S 6 + tr
(clock polarity = 0)
4 (6)
Delay time, SPInCLK low to SPInSOMI valid
td(SPCL-SOMI)S 6 + tf
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
tv(SPCH-SOMI)S tc(SPC)S – 6 – tr ns
(clock polarity = 0)
5 (6)
Valid time, SPInSOMI data valid after SPInCLK low
tv(SPCL-SOMI)S tc(SPC)S – 6 – tf
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK low
tsu(SIMO-SPCL)S 6
(clock polarity = 0)
6 (6)
Setup time, SPInSIMO before SPInCLK high
tsu(SIMO-SPCH)S 6
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low
tv(SPCL-SIMO)S 6
(clock polarity = 0)
7 (6)
Valid time, SPInSIMO data valid after SPInCLK high
tv(SPCH-SIMO)S 6
(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(5) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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SPInCLK
(clock polarity = 0)

SPInCLK
(clock polarity = 1)

55

SPInSOMI SPISOMI Data Is Valid

SPInSIMO SPISIMO Data

Must Be Valid

Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)

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SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 16)
NO. MIN MAX UNI
T
1 tc(SPC)S Cycle time, SPInCLK (5) 100 256tc(ICLK)
tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
2 (6)
tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
3 (6)
tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)S – 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK)
Valid time, SPInCLK high after SPInSOMI data valid
tv(SOMI-SPCH)S 0.5tc(SPC)S – 6 – tr
(clock polarity = 0)
4 (6)
Valid time, SPInCLK low after SPInSOMI data valid
tv(SOMI-SPCL)S 0.5tc(SPC)S – 6 – tf
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
tv(SPCH-SOMI)S 0.5tc(SPC)S – 6 – tr ns
(clock polarity = 0)
5 (6)
Valid time, SPInSOMI data valid after SPInCLK low
tv(SPCL-SOMI)S 0.5tc(SPC)S – 6 – tf
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK high
tsu(SIMO-SPCH)S 6
(clock polarity = 0)
6 (6)
Setup time, SPInSIMO before SPInCLK low
tsu(SIMO-SPCL)S 6
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
tv(SPCH-SIMO)S 6
(clock polarity = 0)
7 (6)
Valid time, SPInSIMO data valid after SPInCLK low
tv(SPCL-SIMO)S 6
(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC) ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(5) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

SPInCLK
(clock polarity = 0)

SPInCLK
(clock polarity = 1)

SPInSOMI SPISOMI Data Is Valid Data Valid

SPInSIMO SPISIMO Data Must

Be Valid

Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)

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SCIn ISOSYNCHRONOUS MODE TIMINGS - INTERNAL CLOCK

Timing Requirements for Internal Clock SCIn Isosynchronous Mode (1) (2) (3)
(see Figure 17)
(BAUD + 1) (BAUD + 1)
IS EVEN OR BAUD = 0 IS ODD AND BAUD ≠ 0 UNIT
MIN MAX MIN MAX
Cycle time,
tc(SCC) 2tc(ICLK) 224 tc(ICLK) 3tc(ICLK) (224 – 1) tc(ICLK) ns
SCInCLK
Pulse duration,
tw(SCCL) 0.5tc(SCC) – tf 0.5tc(SCC) + 5 0.5tc(SCC) + 0.5tc(ICLK) – tf 0.5tc(SCC) + 0.5tc(ICLK) ns
SCInCLK low
Pulse duration,
tw(SCCH) 0.5tc(SCC) – tr 0.5tc(SCC) + 5 0.5tc(SCC) – 0.5tc(ICLK) – tr 0.5tc(SCC) – 0.5tc(ICLK) ns
SCInCLK high
Delay time,
td(SCCH-TXV) SCInCLK high to 10 10 ns
SCInTX valid
Valid time,
SCInTX data
tv(TX) tc(SCC) – 10 tc(SCC) – 10 ns
after SCInCLK
low
Setup time,
tsu(RX-SCCL) SCInRX before tc(ICLK) + tf + 20 tc(ICLK) + tf + 20 ns
SCInCLK low
Valid time,
SCInRX data
tv(SCCL-RX) –tc(ICLK) + tf + 20 –tc(ICLK) + tf + 20 ns
after SCInCLK
low

(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(2) tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

tc(SCC)
tw(SCCH)
tw(SCCL)

SCICLK

tv(TX)
td(SCCHĆTXV)

SCITX Data Valid

tsu(RXĆSCCL)
tv(SCCLĆRX)

SCIRX Data Valid

A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.

Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock

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SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK

Timing Requirements for External Clock SCIn Isosynchronous Mode (1) (2)
(see Figure 18)
MIN MAX UNIT
tc(SCC) Cycle time, SCInCLK (3) 8tc(ICLK) ns
tw(SCCH) Pulse duration, SCInCLK high 0.5tc(SCC) – 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) ns
tw(SCCL) Pulse duration, SCInCLK low 0.5tc(SCC) – 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) ns
td(SCCH-TXV) Delay time, SCInCLK high to SCInTX valid 2tc(ICLK) + 12 + t r ns
tv(TX) Valid time, SCInTX data after SCInCLK low 2tc(SCC) – 10 ns
tsu(RX-SCCL) Setup time, SCInRX before SCInCLK low 0 ns
tv(SCCL-RX) Valid time, SCInRX data after SCInCLK low 2tc(ICLK) + 10 ns

(1) tc(ICLK) = interface clock cycle time = 1/f(ICLK)

(2) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(3) When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).

tc(SCC)
tw(SCCH)
tw(SCCL)

SCICLK
tv(TX)
td(SCCHĆTXV)

SCITX Data Valid

tsu(RXĆSCCL)
tv(SCCLĆRX)

SCIRX Data Valid

A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.

Figure 18. SCIn Isosynchronous Mode Timing Diagram for External Clock

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I2C TIMING
Table 11 assumes testing over recommended operating conditions.

I2C Signals (SDA and SCL) Switching Characteristics (1)

STANDARD MODE FAST MODE
PARAMETER UNIT
MIN MAX MIN MAX
tc(I2CCLK) Cycle time, I2C module clock 75 150 75 150 ns
tc(SCL) Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated START
tsu(SCLH-SDAL) 4.7 0.6 µs
condition)
Hold time, SCL low after SDA low (for a repeated START
th(SCLL-SDAL) 4 0.6 µs
condition)
tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
tw(SCLH) Pulse duration, SCL high 4 0.6 µs
tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns
th(SDA-SCLL) Hold time, SDA valid after SCL low For I2C bus devices 0 3.45 (2) 0 0.9 µs
tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
tr(SCL) Rise time, SCL 1000 20+0.1Cb (3) 300 ns
tr(SDA) Rise time, SDA 1000 20+0.1Cb (3) 300 ns
tf(SCL) Fall time, SCL 300 20+0.1Cb (3) 300 ns
tf(SDA) Fall time, SDA 300 20+0.1Cb (3) 300 ns
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs
tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb (3) Capacitive load for each bus line 400 400 pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) C b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

SDA

tw(SDAH) tw(SP)
tr(SCL) tsu(SDA−SCLH)
tw(SCLL) tsu(SCLH−SDAH)
tw(SCLH)
SCL

tc(SCL) tf(SCL)
th(SCLL−SDAL)
th(SDA−SCLL)
tsu(SCLH−SDAL)
th(SCLL−SDAL)

Stop Start Repeated Stop

A. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
B. The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL
signal.
C. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line tr max + tsu(SDA-SCLH).
D. Cb = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

Figure 19. I2C Timings

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STANDARD CAN CONTROLLER (SCC) MODE TIMINGS

Dynamic Characteristics for the CANSTX and CANSRX Pins

PARAMETER MIN MAX UNIT
td(CANSTX) Delay time, transmit shift register to CANSTX pin (1) 15 ns
td(CANSRX) Delay time, CANSRX pin to receive shift register 5 ns

(1) These values do not include the rise/fall times of the output buffer.

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EXPANSION BUS MODULE TIMING

Expansion Bus Timing Parameters

–40°C ≤ TJ≤ 150°C, 3.0 V ≤ V CC≤ 3.6 V (see Figure 20 and Figure 21)
MIN MAX UNIT
tc(CO) Cycle time, CLKOUT 20.8 ns
td(COH-EBADV) Delay time, CLKOUT high to EBADDR valid 21.4 ns
th(COH-EBADIV) Hold time, EBADDR invalid after CLKOUT high 12.4 ns
td(COH-EBOE) Delay time, CLKOUT high to EBOE fall 11.4 ns
th(COH-EBOEH) Hold time, EBOE rise after CLKOUT high 11.4 ns
td(COL-EBWR) Delay time, CLKOUT low to write strobe (EBWR) low 11.3 ns
th(COL-EBWRH) Hold time, EBWR high after CLKOUT low 11.6 ns
tsu(EBRDATV-COH) Setup time, EBDATA valid before CLKOUT high (READ) (1) 15.2 ns
th(COH-EBRDATIV) Hold time, EBDATA invalid after CLKOUT high (READ) (–14.7) ns
td(COL-EBWDATV) Delay time, CLKOUT low to EBDATA valid (WRITE) (2) 16.1 ns
th(COL-EBWDATIV) Hold time, EBDATA invalid after CLKOUT low (WRITE) 14.7 ns
SECONDARY TIMES
td(COH-EBCS0) Delay, CLKOUT high to EBCS0 fall 13.6 ns
th(COH-EBCS0H) Hold, EBCS0 rise after CLKOUT high 13.2 ns
tsu(COH-EBHOLDL) Setup time, EBHOLD low to CLKOUT high (1) 10.9 ns
tsu(COH-EBHOLDH) Setup time, EBHOLD high to CLKOUT high (1) 10.5 ns

(1) Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
(2) Valid after CLKOUT goes low for write cycles.

tc(CO)

CLKOUT

th(COH-EBADIV)
td(COH-EBADV)

EBADDR Valid

th(COH-EBRDATIV)
tsu(EBRDATV-COH)

EBDATA Valid

th(COH-EBOEH)
td(COH-EBOE)

EBOE

td(COH-EBCS0) th(COH-EBCS0H)

EBCS0

tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)

EBHOLD

1 Hold State

Figure 20. Expansion Memory Signal Timing - Reads

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tc(CO)

CLKOUT

th(COH-EBADIV)
td(COH-EBADV)

EBADDR Valid

th(COL-EBWDATIV)
td(COL-EBWDATV)

EBDATA Valid

th(COL-EBWRH)
td(COL-EBWR)

EBWR

td(COH-EBCS0) td(COH-EBCS0)

EBCS0

tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)

EBHOLD

1 Hold State

Figure 21. Expansion Memory Signal Timing - Writes

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HIGH-END TIMER (HET) TIMINGS

Minimum PWM Output Pulse Width:

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

Minimum Input Pulses that Can Be Captured:

The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:
Once the input pulse width is greater than LRP, the resolution of the measurement is
still HRP. (That is, the captured value gives the number of HRP clocks inside the
pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK

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MULTI-BUFFERED A-TO-D CONVERTER (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on V
SS and V CC , from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD
REFLO unless otherwise noted.

Resolution 10 bits (1024 values)

Monotonic Assured
Output conversion code 00h to 3FFh [00 for VAI ≤ AD REFLO ; 3FF for VAI ≥ AD REFHI ]

Table 17. MibADC Recommended Operating Conditions (1)

MIN MAX UNIT
ADREFHI A-to-D high-voltage reference source VSSAD VCCAD V
ADREFLO A-to-D low-voltage reference source VSSAD VCCAD V
VAI Analog input voltage VSSAD – 0.3 VCCAD + 0.3 V
Analog input clamp current (2)
IAIC –2 2 mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

(1) For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 18. Operating Characteristics over Full Ranges of Recommended Operating Conditions (1) (2)
PARAMETER DESCRIPTION/CONDITIONS MIN TYP MAX UNIT
RI Analog input resistance See Figure 22. 250 500 Ω
Conversion 10 pF
CI Analog input capacitance See Figure 22.
Sampling 30 pF
IAIL Analog input leakage current See Figure 22. –1 1 µA
IADREFHI ADREFHI input current ADREFHI = 3.6 V, ADREFLO = VSSAD 5 mA
Conversion range over which
CR ADREFHI - ADREFLO 3 3.6 V
specified accuracy is maintained
Difference between the actual step width
EDNL Differential nonlinearity error ±1.5 LSB
and the ideal value. See Figure 23.
Maximum deviation from the best straight
line through the MibADC. MibADC transfer
EINL Integral nonlinearity error ±2 LSB
characteristics, excluding the quantization
error. See Figure 24.
Maximum value of the difference between
E TOT Total error/Absolute accuracy an analog value and the ideal midstep ±2 LSB
value. See Figure 25.

(1) VCCAD = ADREFHI

(2) 1 LSB = (ADREFHI - ADREFLO)/210 for the MibADC

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External
MibADC
Rs Input Pin Ri Sample Switch

Parasitic Sample R leak

V src Capacitance Capacitor

Ci

Figure 22. MibADC Input Equivalent Circuit

Table 19. Multi-Buffer ADC Timing Requirements

MIN NOM MAX UNIT
tc(ADCLK) Cycle time, MibADC clock 0.05 µs
td(SH) Delay time, sample and hold time 1 µs
td©) Delay time, conversion time 0.55 µs
td(SHC) (1) Delay time, total sample/hold and conversion time 1.55 µs

(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
















 !

  






  !


   




 

 
 


A. 1 LSB = (ADREFHI - ADREFLO)/210

Figure 23. Differential Nonlinearity (DNL)

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The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.

0 ... 111

0 ... 110 Ideal

Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
0 ... 011
(ć 1/2 LSB)

0 ... 010
End-Point Lin. Error

0 ... 001 At Transition

001/010 (ć 1/4 LSB)
0 ... 000
0 1 2 3 4 5 6 7
Analog Input Value (LSB)

A. 1 LSB = (ADREFHI - ADREFLO)/210

Figure 24. Integral Nonlinearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the
difference between an analog value and the ideal midstep value.
















 
    


   





 


     
 



  

 
 


A. 1 LSB = (ADREFHI - ADREFLO)/210

Figure 25. Absolute Accuracy (Total) Error

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Thermal Resistance Characteristics

PARAMETER °C/W
Rθ JA 43
Rθ JC 5

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Revision History
This revision history highlights the changes made to the device-specific datasheet SPNS109.

Table 12. Revision History

SPNS109 to SPNS109A
Added note to PORRST Timing Diagram.
Changed TA range to –40°C to 85°C on twec in "Timing Requirements for Program Flash" table.
Changed twec MIN value to 50000 and deleted TYP value in "Timing Requirements for Program Flash" table.
Changed terase(sector) TYP value to 1.7 in "Timing Requirements for Program Flash" table.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TMS470R1B1MPGEA NRND Production LQFP (PGE) | 144 60 | JEDEC Yes NIPDAU Level-3-260C-168 HR - R1B1MPGEA
TRAY (5+1) TMS470
TMS470R1B1MPGEA.A NRND Production LQFP (PGE) | 144 60 | JEDEC Yes NIPDAU Level-3-260C-168 HR See R1B1MPGEA
TRAY (5+1) TMS470R1B1MPGEA TMS470
TMS470R1B1MPGEAR NRND Production LQFP (PGE) | 144 500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR - R1B1MPGEA
TMS470
TMS470R1B1MPGEAR.A NRND Production LQFP (PGE) | 144 500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR See R1B1MPGEA
TMS470R1B1MPGEAR TMS470

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
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Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TMS470R1B1MPGEA PGE LQFP 144 60 5X12 150 315 135.9 7620 25.4 17.8 17.55
TMS470R1B1MPGEA.A PGE LQFP 144 60 5X12 150 315 135.9 7620 25.4 17.8 17.55

Pack Materials-Page 1
 MECHANICAL DATA

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996

PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK

108 73

109 72

0,27
0,08 M
0,17

0,50

144 0,13 NOM

37

1 36
Gage Plane
17,50 TYP
20,20 SQ
19,80 0,25
22,20 0,05 MIN 0°– 7°
SQ
21,80

0,75
0,45
1,45
1,35

Seating Plane

1,60 MAX 0,08

4040147 / C 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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