VLSI Digital Circuits
Lecture 13: Static Sequential
Circuits
[Adapted from Prof. Mary Jane Irwin’s slides, Rabaey’s Digital Integrated
Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Sequential Logic
Inputs Outputs
Combinational
Logic
Current Next
Registers
State State State
clock
Timing Metrics
In D Q Out
clock
clock
tsu thold time
In data
stable
tc-q time
Out output output
stable stable
time
System Timing Constraints
Inputs Outputs
Combinational
Logic
Current Next
Registers
State State
State
T (clock period)
clock
tcdreg + tcdlogic thold T tc-q + tplogic + tsu
Static vs Dynamic Storage
Static storage
preserve state as long as the power is on
have positive feedback (regeneration) with an internal
connection between the output and the input
useful when updates are infrequent (clock gating)
Dynamic storage
store state on parasitic capacitors
only hold state for short periods of time (milliseconds)
require periodic refresh
usually simpler, so higher speed and lower power
Latches vs Flipflops
Latches
level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode
input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode
Flipflops (edge-triggered)
edge sensitive circuits that sample the inputs on a clock
transition
- positive edge-triggered: 0 1
- negative edge-triggered: 1 0
built using latches (e.g., master-slave flipflops)
Positive and Negative Latches
In D Q Out In D Q Out
clock clock
clk clk
In In
Out Out
Review: The Regenerative Property
Vi1 Vo1 Vi2 Vo2
cascaded inverters
Vi2 = Vo1
A If the gain in the transient
region is larger than 1,
C
only A and B are stable
operation points. C is a
metastable operation
B point.
Vi1 = Vo2
Bistable Circuits
The cross-coupling of two Vi1
inverters results in a bistable
circuit (a circuit with two Vi2
stable states)
Have to be able to change the stored value by making A
(or B) temporarily unstable by increasing the loop gain to
a value larger than 1
done by applying a trigger pulse at Vi1 or Vi2
the width of the trigger pulse need be only a little larger than the
total propagation delay around the loop circuit (twice the delay of
an inverter)
Two approaches used
cutting the feedback loop (mux based latch)
overpowering the feedback loop (as used in SRAMs)
Review: SR Latch
S R Q !Q
S 0 0 Q !Q memory
!Q
1 0 1 0 set
0 1 0 1 reset
Q
R 1 1 0 0 disallowed
Review: Clocked D Latch
D
!Q
D Latch
Q
D Q
clock
transparent mode clock
clock
hold mode
MUX Based Latches
Change the stored value by cutting the feedback loop
feedback feedback
1 0
Q Q
D 0 D 1
clk clk
Negative Latch Positive Latch
Q = clk & Q | !clk & D Q = !clk & Q | clk & D
transparent when the transparent when the
clock is low clock is high
TG MUX Based Latch Implementation
clk
!clk
input sampled
D (transparent mode)
clk
clk
D Latch
D Q
!clk
clk feedback
(hold mode)
PT MUX Based Latch Implementation
clk !Q
D Q
input sampled
(transparent mode)
!clk
Reduced area and clock clk
load, but a threshold drop
!clk
at output of pass transistors
so reduced noise margins
and performance feedback
(hold mode)
Master Slave Based ET Flipflop
D FF
D Q
0
1 Q clock
1
QM
D 0
clk clk
clk
Slave D
Master
clk = 0 transparent hold QM
clk = 01 hold transparent Q
MS ET Implementation
Master Slave
I2 T2 I3 I5 T4 I6 Q
QM
I1 T1 I4 T3
D
clk
master transparent master hold
slave hold slave transparent
clk
!clk
MS ET Timing Properties
Assume propagation delays are tpd_inv and tpd_tx, that
the contamination delay is 0, and that the inverter
delay to derive !clk is 0
Set-up time - time before rising edge of clk that D
must be valid
tsu = 3 * tpd_inv + tpd_tx
Propagation delay - time for QM to reach Q
tc-q = 2*tpd_inv + tpd_tx
Hold time - time D must be stable after rising edge of
clk t = zero
hold
Set-up Time Simulation
3
Q
2.5
2 tsu = 0.21 ns
QM
1.5 tsetup
Volts
1 D clk
0.5
I2 out
0
-0.5 works correctly
0 0.2 0.4 0.6 0.8 1
Time (ns)
Set-up Time Simulation
3
Q
2.5
I2 out tsu = 0.20 ns
2
1.5 tsetup
Volts
1 D clk
0.5
QM
0
-0.5 fails
0 0.2 0.4 0.6 0.8 1
Time (ns)
Propagation Delay Simulation
2.5
2 tc-q(LH) = 160 psec
1.5
Volts
1 tc-q(LH) tc-q(HL) = 180 psec
tc-q(HL)
0.5
-0.5
0 0.5 1 1.5 2 2.5
Time (ns)
Power PC Flipflop
!clk clk
1D Q 0 1
0 1 1 0 1 0
clk !clk
master transparent master hold
slave hold slave transparent
clk
!clk
Reduced Load MS ET FF
Clock load per register is important since it directly
impacts the power dissipation of the clock network.
Can reduce the clock load (at the cost of robustness) by
making the circuit ratioed
clk !clk
I1 I3
QM
D T1 T2 Q
I2 I4
!clk clk
reverse conduction
to switch the state of the master, T1 must be sized to overpower I2
to avoid reverse conduction, I4 must be weaker than I1
Non-Ideal Clocks
clk clk
!clk !clk
Ideal clocks Non-ideal clocks
clock skew
1-1 overlap
0-0 overlap
