Ratioed Logic
(will come back to
logical effort
concept later)
1
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Ratioed Logic
VDD VDD VDD
Resistive Depletion PMOS
Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
2
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Ratioed Logic
VDD
• N transistors + Load
Resistive
• VOH = V DD
Load RL
• VOL = RPN
F RPN + RL
In1 • Assymetrical response
In2 PDN
In3 • Static power consumption
• tpL= 0.69 RLCL
VSS
3
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
depletion load NMOS pseudo-NMOS
4
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Pseudo-NMOS
VDD
F
CL
A B C D
VOH = VDD (similar to complementary CMOS)
V OL 2 kp
2
k n VDD – V Tn V OL – ------------- = ------ V DD – VTp
2 2
kp
V OL = VDD – V T 1 – 1 – ------ (assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
5
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Pseudo-NMOS VTC
3.0
2.5
2.0 W/Lp = 4
1.5
Vout [V]
W/Lp = 2
1.0
W/Lp = 0.5 W/Lp = 1
0.5
W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Improved Loads
VDD
M1 M1 >> M2
Enable M2
CL
A B C D
Adaptive Load
7
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Improved Loads (2) PDN are mutually
exclusive
VDD VDD Logic function and its
inverse are both
implemented
M1 M2 Assume Out and Out_bar a
initially high and low
Out Out Now making PDN1 conduc
A Fight between PDN1 and M
A PDN1 PDN2
B Out_bar is high-impedance
B
PDN1 musst be stronger th
VSS VSS M1
Differential Cascode Voltage Switch Logic (DCVSL)
8
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
DCVSL Transient Response
NAND-AND Gate
2.5
AB
V ol ta ge[V]
1.5
AB
A,B
0.5 A,B
-0.50 0.2 0.4 0.6 0.8 1.0
Implement 0 in out branch Time [ns]
Implement dual in out_bar branch
9
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Pass-Transistor
Logic
10
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Pass-Transistor Logic
Switch Out A
Out
Inputs
Network B
B
• N transistors
• No static consumption
Re-generation is tricky!!!
11
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Example: AND Gate
B
A
B
F = AB
12
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
13
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
NMOS-Only Logic
3.0
In
In
1.5 m/0.25 m Out
2.0
Voltage [V]
VD D x x
Out
0.5 m/0.25 m
0.5 m/0.25 m 1.0
0.0
0 0.5 1 1.5 2
Time [ns]
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
NMOS-only Switch
C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1
VB does not pull up to 2.5V, but 2.5V - VTN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
NMOS Only Logic:
Level Restoring Transistor (SOLUTION #1)
VDD
VDD
Level Restorer
Mr
B
M2
X
A Mn Out
M1
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem 16
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Solution 2: Single Transistor Pass Gate with VT=0
VDD
VDD
0V 2.5V
VDD 0V Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Complementary Pass Transistor Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network
B B B B B B
A A A
B F=AB B F=A+B A F=AÝ
A A A
(b)
B F=AB B F=A+B A F=AÝ
AND/NAND OR/NOR EXOR/NEXOR
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Solution 3: Transmission Gate
C
C
A B A B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Resistance of Transmission Gate
30
2.5 V
Rn Rn
Rp
Resistance, ohms
20
2.5 V Vou t
Rp
0V
10
Rn || Rp
0
0.0 1.0 2.0
Vou t , V
20
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Pass-Transistor Based Multiplexer
S S
VDD
VDD
S
A
M2
S F
M1
B
GND
In1 S S In2
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
QUIZ
Design a 2:1 multiplexer whose propagation delay is
0.69nsec.
You have NMOS(s) whose RN=1k
PMOS(s) whose Rp=2k
CL=1pF
You have inverters whose delay is 0.1nsec.
Output of the mux must be regenerative.
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Delay in Transmission Gate Networks
2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req
V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req
In
C CC C C CC C
(c)
23
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Dynamic Logic
24
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Dynamic CMOS
In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage
of signal values on the capacitance of high
impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
25
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Dynamic Gate
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL
28
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging C L
29
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Properties of Dynamic Gates
Overall power dissipation usually higher than static
CMOS
no static current path ever exists between VDD and GND
(including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock 30
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Issues in Dynamic Design 1: Charge
Leakage
CLK
Clk Mp
Out
A CL
VOut Evaluate
Clk Me
Precharge
Leakage sources
Dominant component is subthreshold current
31
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Solution to Charge Leakage
Keeper
Clk Mp Mkp
A Out
CL
B
Clk Me
Same approach as level restorer for pass-transistor logic
32
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Issues in Dynamic Design 2: Charge
Sharing
Charge stored originally on
Clk Mp CL is redistributed (shared)
Out
over CL and CA leading to
A CL reduced robustness
B=0 CA
Clk Me CB
33
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Issues in Dynamic Design 4: Clock
Feedthrough
Coupling between Out and
Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.
34
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Clock Feedthrough
Clock feedthrough
Clk
Out 2.5
In1
In2 Voltage 1.5
In3 In &
0.5 Clk
In4 Out
Clk -0.5
0 0.5 Time, ns 1
Clock feedthrough
35
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
36
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
QUIZ
Find tpHL in two cases,
critical path
C1=C2=CL=10fF,
RN=1k,
In3 1 M3 CL 1.in3 and in2 have
arrived earlier and in1
In2 1 M2 C2 charged arrives late i.e. 200ps
In1 M1 C1 charged after in3 and in2
01
2.In1 and in2 have
arrived, in3 arrives 200ps
later.
37
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
