Designing Static CMOS

Logic Circuits

1
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Static CMOS Circuits

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).

2
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 PDN
…

NMOS only
InN

PUN and PDN are logically dual logic networks

3
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

4
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

5
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Threshold Drops
VDD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D

6
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Complementary CMOS Logic Style

7
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Example Gate: NAND

8
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Example Gate: NOR

9
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

10
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Constructing a Complex Gate

 Logic Dual need not be Series/Parallel Dual

 In general, many logical dual exist, need to
choose one with best characteristics
 Use Karnaugh-Map to find good duals
 Goal: find 0-cover and 1-cover with best parasitic
or layout properties
 Maximize connections to power/ground
 Place critical transistors closest to output node

11
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Carry Gate
C C’
 F = (ab+bc+ac)’
AB 0 0  Carry ‘c’ is critical
 Factor c out:
AB’ 0 1  F=(ab+c(a+b))’
 0-cover is n-pd
A’B’ 1 1
 1-cover is p-pu
A’B 0 1

12
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Carry Gate (2)

f'  Pull Down is easy

 Order by maximizing
a c
connections to
ground and critical
a transistors
b b
 For pull up – Might
guess series dual–
would guess wrong

13
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Carry Gate (3)

a b  Series/Parallel Dual
 3-series transistors
 2 connections to
c a Vdd
 7 floating capacitors
b
f'

14
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Carry Gate (4)

 Pull Up from 1 cover

of Kmap
a a b  Get a’b’+a’c’+b’c’
 Factor c’ out
 3 connections to
b c Vdd
 2 series transistors
f'
 Co-Euler path layout
 Moral: Use Kmap!

15
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Cell Design

 Standard Cells
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width

16
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Standard Cell Layout
Methodology – 1980s

Routing
channel
VDD

signals

GND

17
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Standard Cell Layout
Methodology – 1990s
Mirrored Cell

No Routing VDD
channels
VDD

M2

M3
GND
Mirrored Cell GND
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© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is “12 pitch”

Out
In
2

Rails ~10
GND
Cell boundary

19
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
With minimal VDD With silicided VDD
diffusion diffusion
routing

VDD

M2
Out In Out
In
In Out

M1

GND GND

20
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
VDD 2-input NAND gate
VDD

B
A B

Out
A

GND

21
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Stick Diagrams

Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

22
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Stick Diagrams

Logic Graph X PUN

A
j C
B C

X i VDD
X = C • (A + B)
C
i B j A

A B
PDN
A GND
B
C

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© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Two Versions of C • (A + B)

A C B A B C

VDD VDD

X X

GND GND

24
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Consistent Euler Path

X i VDD

B j A

GND A B C

25
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 OAI22 Logic Graph

X PUN
A C

B D D C

X VDD
X = (A+B)•(C+D)

C D
B A

A B PDN
A GND
B
C
D

26
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Example: x = ab+cd
x x

b c b c

x VDD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VD D

GND
a b c d
(c) stick diagram for ordering {a b c d}

27
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
Properties of Complementary CMOS
Gates Snapshot

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

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© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 CMOS Properties
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power and
ground; no static power dissipation
 Propagation delay function of load capacitance
and resistance of transistors
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© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

30
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Input Pattern Effects on Delay

 Delay is dependent on
Rp Rp the pattern of inputs
A B  Low to high transition
 both inputs go low
Rn CL – delay is 0.69 Rp/2 CL
B  one input goes low
– delay is 0.69 Rp CL
Rn
Cint
A
 High to low transition
 both inputs go high
– delay is 0.69 2Rn CL

31
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Delay Dependence on Input Patterns

3
Input Data Delay
2.5 A=B=10
Pattern (psec)
2 A=B=01 67
A=1 0, B=1
A=1, B=01 64
Voltage [V]

1.5

1
A=1, B=10 A= 01, B=1 61

0.5 A=B=10 45

0 A=1, B=10 80
0 100 200 300 400 A= 10, B=1 81
-0.5
time [ps] NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF 32
© Forrest
EE141 Brewer and © Digital Integrated Circuits2nd
Combinational Circuits
 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

33
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Multi-Fingered Transistors
One finger Two fingers (folded)

Less diffusion capacitance

34
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Transistor Sizing a Complex
CMOS Gate

B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

35
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fan-In Considerations

A B C D

A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
36
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a
750
fan-in
tp (psec)

tpHL tp greater than

500
4 should be
250 tpLH avoided.
linear
0
2 4 6 8 10 12 14 16
fan-in

37
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 tp as a Function of Fan-Out

All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)

Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out

38
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 tp as a Function of Fan-In and Fan-
Out

 Fan-in: quadratic due to increasing

resistance and capacitance
 Fan-out: each additional fan-out gate
adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

39
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Practical Optimization

 The previous arguments regarding tp raise the

question – why build nor at all?
 Criticality is not a path– but a transition so it is usually only
on rising or falling (but not both)
 NOR forms have bad pull-up but good pull down
 NAND forms have bad pull-down but good pull up
 Determine the critical transition(s) and design for them–
using Elmore or Simulation on the appropriate edge only!
 Logical Effort presupposes uniform rise and fall times, so
good in general, but can be beat
 Static Timing Analyzers nearly always get this wrong!

40
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 1
 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
41
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 2
 Transistor ordering
critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL
42
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 3
 Alternative logic structures
F = ABCDEFGH

43
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 4
 Isolating fan-in from fan-out using buffer
insertion

CL CL

44
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 5
 Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

 linear reduction in delay
 also reduces power consumption
 But the following gate may be much slower!
 Large fan-in/fan-out requires use of “sense
amplifiers” to restore the signal (memory)

45
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Sizing Logic Paths for Speed

 Frequently, input capacitance of a logic path

is constrained
 Logic also has to drive some capacitance
 Example: ALU load in an Intel’s
microprocessor is 0.5pF
 How do we size the ALU datapath to achieve
maximum speed?
 We have already solved this for the inverter
chain – can we generalize it for any type of
logic?
46
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Buffer Example

In Out

1 2 N CL

N
Delay    pi  g i  f i  (in units of inv)
i 1

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
47
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort
 CL 
Delay  k  Runit Cunit 1  
 Cin 
  p  g  f 
p – intrinsic delay (3kRunitCunit) - gate parameter  f(W)
g – logical effort (kRunitCunit) – gate parameter  f(W)
f – effective fanout

Normalize everything to an inverter:

ginv =1, pinv = 1

Divide everything by inv

(everything is measured in unit delays inv)
Assume = 1.
© Forrest
EE141 Brewer and © Digital Integrated Circuits2nd
48
Combinational Circuits
 Delay in a Logic Gate

Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay:
h=gf

logical effective fanout =

effort Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
49
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort

 Inverter has the smallest logical effort and

intrinsic delay of all static CMOS gates
 Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
 Logical effort increases with the gate
complexity

50
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD VDD VDD

A 2 A 2 B 2 B 4

F
F
A 4
A 2
A 1 F

A 1 B 1
B 2

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

51
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort of Gates

t pNAND
Normalized delay (d)

g= t pINV
p=
d=
g=
p=
d=

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

52
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort of Gates

t pNAND
Normalized delay (d)

g = 4/3 t pINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

53
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Add Branching Effort

Branching effort:

Con  path  Coff  path

b
Con  path

54
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Multistage Networks
N
Delay    pi  g i  f i 
i 1

Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = di = pi + hi
55
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Optimum Effort per Stage

When each stage bears the same effort:

hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i  h g i

Minimum path delay

Dˆ   g i f i  pi   NH 1/ N  P

56
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing

D  NH 1/ N
 Npinv
D
  H 1/ N ln H 1/ N  H 1/ N  pinv  0
N
1 / Nˆ
Substitute ‘best stage effort’ hH

57
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Logical Effort

From Sutherland, Sproull

58
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Method of Logical Effort

 Compute the path effort: F = GBH

 Find the best number of stages N ~ log4F

 Compute the stage effort f = F1/N

 Sketch the path with this number of stages
 Work either from either end, find sizes:
Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

59
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Optimize Path

1 b c
a 5

g=1 g = 5/3 g = 5/3 g=1

f=a f = b/a f = c/b f = 5/c

Effective fanout, F =
G=
H=
h=
a=
b=
60
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Optimize Path

1 b c
a 5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
61
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example: Optimize Path

1 b c
a 5

g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59
62
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Example – 8-input AND

63
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Summary

Sutherland,
Sproull
Harris

64
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits
 Homework 5
1. Using the Carry cell design from earlier homework, optimally size the
carry propagate chain for a 16-bit adder to minimize worst case
delay where Cin is driven by a 1u/0.6u inverter and Cout drives a
fanout of 4 such loads. (use logic effort, show your work!)
2. For the problems below, use parameters from class for 0.5um and
use 2x voltages as applicable. Chap 5: problems: 4, 7, 8, 15
3. Chap 6, problems: 2, 4, 5, 7
4. Design the parity tree: c = a xor b xor c xor d in Complementary
Pass Transistor Logic, insert inverters to restore the output swing –
Given input drive from an inverter stage, and an inverter every 2
stages of logic, and inverter output restore, estimate the propagation
time for devices using the AMI 0.5um model.
New (digital) AMI model (for minimum length only!):
n-channel: VT=0.77, =0.03, Vsat=1.56V, k=32A/V2
p-channel: VT=-0.95, =0.03 Vsat=2.8V, k=-16A/V2

65
© Forrest
EE141 Brewer and © Digital Integrated Circuits 2nd
Combinational Circuits