Digital Design

Course Code: CSET105

Unit – II:
Design and Analysis of Combinational Circuits
Topic: Combinational Circuits
Course Instructor
Dr. Abhimanyu Bar
 Logic Design
• Logic design refers to the process of designing digital
circuits that perform a specified logical function.

• Digital circuits are composed of logic gates, which

are the building blocks for constructing more complex
digital systems.

• Logic design involves designing the structure and

interconnection of these gates to implement desired
logical functions

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Examples of Circuits Layout

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 Lect-17
Required Preliminaries.....

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Logic Gates
• A logic gate is a device that acts as a building block for digital circuits.
• They perform basic logical functions that are fundamental to digital
circuits.
Basic Gates

NOT Gate

AND Gate

OR Gate
Basic Logic Gates: NOT Gate
Block Diagram Verilog Code
Boolean Expression

Truth Table
Basic Logic Gates: Buffer
Basic Logic Gates: AND Gate Verilog Code
Block Diagram Boolean Expression

Truth Table
Basic Gates: OR Gate Verilog Code
Block Diagram

INPUT OUTPUT
A B A B
0 0 0
0 1 1
1 0 1
1 1 1
INPUT OUTPUT
A B A+B
0 0 0
0 1 1
1 0 1
1 1 (Carry 1) 0
Universal Logic Gates
• Universal logic gates are the logic gates that can implement any Boolean
function without requiring any other type of gate.
• They are called as “Universal Gates” because-
- They can realize all the binary operations.
- All the basic logic gates can be derived from them.
• There are following two universal logic gates-
NAND
NOR
Universal Gates: NAND Gate Verilog Code
Universal Gates: NOR Gate Verilog Code
Other / Exclusive Gates
• Have a special purpose of its implementation
• Used for Mathematical Operation and Code Conversion
• Exclusive-OR or simply XOR Gate:
• Exclusive-NOR or simply XNOR:

XOR
XNOR
XOR Gate
XNOR Gate
 Block Diagram

Everyone need to verify

using the truth table of the
expressions after getting the
timing diagram or gtkwave
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Similar Circuit Representation

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AND-OR to NAND - NAND Realization

AND-OR Realization

NAND-NAND Realization
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 Homework:
OR-AND to NOR-NOR Realization

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XOR and XNOR from NAND and NOR
•
Making a Circuit from Truth-Table
•
Combinational Logic Circuits
 Logic Design
• A logic circuit is a circuit that
executes a processing or controlling
function in a computer.
OR
• A circuit for performing logical
operations on input signals to
produce desired output
• Implemented using logic gates
• Behavior is given by truth table
Hardware Realization of Circuits

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Example: Binary to Gray Code Conversion Circuit Diagram

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Example: Gray Code to Binary Conversion Circuit Diagram

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Hardware Realization of Circuits

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Points to be Remember while Designing a Circuit

1. Proper logic Gates Selection: Which Gate is appropriate for efficiently replicate the requirement of
the problem.

2. Propagation Delay: Minimize overall propagation delay to improve the circuit's speed and
responsiveness.

3. Gate Arrangement: Pay attention to the order and arrangement of gates to achieve the intended logical
operation.

4. Power Consumption: Optimize the circuit design to reduce power consumption where possible.
5. Testing and Simulation: Simulate the circuit using software tools to verify its correctness using
physical implementation and Truth Table.

6. Modularity and Hierarchy:

i. If the circuit is part of a larger system, design it with modularity and hierarchy in mind.
ii. Encapsulate functional blocks into separate modules for easier maintenance and scalability.

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Classifications of Logic Circuits
 Logic circuits are broadly classified into two types

Combinational Logic Circuits Sequential Logic Circuits

Combinational Logic Circuits
 Combinational Logic Circuits
 The circuits that contain different types of logic gates are called as Combinational Logic Circuit or
Combinational Circuit(CC).
 The output of the combinational circuit is determined from the present combination of inputs,
regardless of the previous input.
 The input variables, logic gates, and output variables are the basic components of the combinational
logic circuit.
 In combinational circuits, output of the given circuit, at a given time, is dependent only on the input
present at that time. Which means, there is no requirement of memory element in designing of
combinational circuits.

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Design Procedure of Combinational Circuit
 Any combinational circuit can be designed by the following steps of design
procedure.
1. The problem statement.

2. Identify the number of input and output variables.

3. The input and output variables are assigned with letter symbols.

4. Construction of a truth table for the given logic.

5. The simplified Boolean expression is obtained by any method of minimization, such

as Boolean Axioms/Rules or Karnaugh-Map.

6. A logic diagram is realized from the simplified Boolean expression using logic
gates.
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EXAMPLE-1
 Design a combinational circuits with three input variables
that will produce a logic-1 output when more than one
input variables are HIGH state.
Solution:
STEP1: The problem statement.
Design a combinational circuits with three input variables that
will produce a logic-1 Output when more than one input variables are
HIGH.
STEP2: Identify the input and output variables
1. No. of inputs required: 3
2. No. of output required: 1
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EXAMPLE-1…

STEP3: The input & outputs are

assigned with letter symbols
 Letter symbol for inputs: A, B, C
 Letter symbol for output: Y

STEP4: Construction of a truth table for

the given logic

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EXAMPLE-1…

STEP5: Obtain the simplified expression

for output variable using K-map
simplification.

Y = (AB)+(AC)+(BC)

STEP6: A logic diagram is realized from

the simplified Boolean expression using
logic gates
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Practice Questions….. ?
 Design a circuit with 4 inputs that has outputs with a binary value equal to
the number of inputs that are HIGH.

 A logic circuit accepts two 3-bit numbers and generates a logic output
only when the two 3-bit numbers applied to the circuit are equal. Design
the logic circuit.

 Design a logic circuit that will produce a 1 only when the number of 1’s in
a set of four inputs variables, A, B, and C, D are even (i.e. an even parity
checker).
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Combinational Logic Circuits Classification
 Binary Adder
1. Half Adder
2. Full Adder
3. FA using HA
4. Parallel Adder

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Half Adder
Half Adder
 Half Adder is a combinational logic circuit to calculate the arithmetic binary addition of two single-bit
numbers.
 It is designed by connecting one EX-OR gate and one AND gate.
 The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and a
sum.
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

 The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum: S = A’B+ AB’= AB
Carry:C = A . B
Half Adder Circuit Diagram
Sum, S = A’B+ AB’= AB
Carry, C = A . B

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Full Adder
Full Adder
 It is a combinational circuit that adds two single bit number along with the
carry bit generated from previous position and gives sum bit and carry bit
to the next position as an output.

 So, full adder circuit contain 3 input and 2 output as shown in the truth
table.

 To get the Boolean expression for the sum and carry bit we need to solve 2
K-maps
Full Adder: Add 1-bit + 1-Bit+ 1-Bit = ?

Inputs Outputs
Sum Carry
A B Cin
(S) (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Full Adder Circuit Realization
Sum: S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry: Cout = AB+ ACin + BCin

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Full Adder using 2-Half Adder
 Full Adder using XOR and OR gate
 The Boolean expressions for the SUM and CARRY outputs are given by the equations,
 Sum: S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
 Carry: Cout = AB+ ACin + BCin
 The logic diagram of the full adder can also be implemented with two half-adders and one OR gate.
 The S output from the second half adder is the exclusive-OR of C in and the output of the first half-adder

Cout = AB+ ACin+ BCin.

S = A’BC’in + AB’C’in + ABCin + A’B’Cin . = AB+ ACin+ BCin (A +A’)
= ABCin+ AB+ ACin+ A’BCin
= C’in (A’B+AB’) + Cin (AB+A’B’) = AB (Cin+1) + ACin+ A’BCin [Cin+1= 1]
= C’in (A’B+AB’) + Cin (A’B+AB’)’ = AB+ ACin+ A’BCin
= AB+ ACin (B+B’) + A’BCin
= Cin  (A’B+AB’) = ABCin+ AB+ A’BCin+ AB’Cin
= AB (Cin+1) + A’BCin+ AB’Cin [Cin+1= 1]
= Cin  (A  B) [x  y = x’y+ xy’] = AB+ A’BCin+ AB’Cin
= AB+ Cin (A’B+AB’)

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Full Adder using XOR and OR gate Circuit
 Sum: S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
= Cin  (A  B)
 Carry: Cout = AB+ ACin + BCin
= AB+ Cin (A’B+AB’)

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Full Adder using 2-XOR and 1-OR Gate

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 Homework:
Implementation of Full Adder using NAND gates
Note: This is not the exact circuit Diagram of the Required FA, Replace the figure with proper diagram
using NAND Gate

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 Homework:
Implementation of Full Adder using NOR gates
Note: This is not the exact circuit Diagram of the Required FA, Replace the figure with proper diagram
using NOR Gate

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Parallel Adder
 Parallel Adder:
Ripple Carry Adder/Carry Propagation Adder

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About the Full Adders
There are different types of full adders are possible:
Ripple Carry Adder
Carry Look Ahead Adder
BCD Adder
Serial Adder & etc.

Adders can be used in:

Digital Diaries
Digital Calculator
Digital Computer
Arithmetic Logic Unit (ALU) of Microprocessors.
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Binary Subtractor
1. Half Subtractor
2. Full Subtractor
3. FS using HS
Half Subtractor Truth Table:

 The half-subtractor is a combinational

circuit which is used to perform
subtraction of two bits.
 It has two inputs, A (minuend) and B
(subtrahend) and two outputs Difference
and Borrow.
 The BORROW output here specifies
whether a ‘1’ has been borrowed to perform
the subtraction.
 Half Subtractor…
 K-map simplification for half Subtractor:

 The Boolean expressions for the DIFFERENCE and BORROW outputs are given by the equations,
Difference, D = A’B+ AB’= A  B
Borrow, Bout = A’ . B

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Full Subtractor
A full Subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also
takes into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower
minuend bit or not.

As a result, there are three bits to be handled at the input of a full Subtractor, namely the two bits to be
subtracted and a borrow bit designated as Bin.

There are two outputs, namely the DIFFERENCE output D and the BORROW output Bout. The
BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from the next possible higher
minuend bit.

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 Full Subtractor
Inputs Outputs  K-map simplification for full Subtractor:
Difference Borrow
A B Bin
(D) (Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

 The Boolean expressions for the DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D = A’B’Bin+ A’BB’in + AB’B’in + ABBin
Borrow, Bout = A’B+ A’Bin + BBin .

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Full Subtractor Circuit Realization
 The Boolean expressions for the DIFFERENCE and BORROW outputs are given by the equations,
Difference, D = A’B’Bin+ A’BB’in + AB’B’in + ABBin
Borrow, Bout = A’B+ A’Bin + BBin .

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 Full Subtractor using XOR and OR gate
 The logic diagram of the full Subtractor can also be implemented with two half Subtractor and one
OR gate.
 The difference, D output from the second half Subtractor is the exclusive-OR of B in and the output
of the first half Subtractor, giving
Borrow, Bout = A’B+ BBin+ A’Bin.
= A’B+ BBin+ A’Bin (B +B’)
= A’BBin+ A’B+ BBin+ A’B’Bin
Difference, D = A’BB’in + AB’B’in + ABBin + A’B’Bin . = A’B (Bin+1) + BBin+ A’B’Bin [Bin+1= 1]
= B’in (A’B+AB’) + Bin (AB+A’B’) = A’B+ BBin+ A’B’Bin
= B’in (A’B+AB’) + Bin (A’B+AB’)’ [(x’y+xy’)’= = A’B+ BBin (A+A’) + A’B’Bin [A+A’= 1]
(xy+x’y’)] = A’BBin+ A’B+ ABBin+ A’B’Bin
= Bin  (A’B+AB’)
= A’B (Bin+1) + ABBin+ A’B’Bin [Bin+1= 1]
= Bin  (A  B) [x  y = x’y+ xy’]
= A’B+ ABBin+ A’B’Bin
= A’B+ Bin (AB+A’B’)

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 Full Subtractor using XOR and OR Gate
or
FS using HS

Difference, D = A’B’Bin+ A’BB’in + AB’B’in + ABBin = Bin  (A  B)

Borrow, Bout = A’B+ A’Cin + BBin . = A’B+ Bin (AB+A’B’)

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 Binary Adder-Subtractor

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 4-Bit Binary Adder-Subtractor
 K = 0 : B ⊕ 0 = B.0’ + B’. 0 = B
 K = 1 : B ⊕ 1 = B.1’ + B’. 1 = B’ then,
i.e.
 If K = 0, then A+B
 If K = 1, then A+ (1’s complement of B) +1 (Carry)
= A+ 2’s complement of B
= A–B
Hence this circuit is called as Adder-Subtractor.

A B K Function
BCD 0011 0 Adder: BCD to Ex-3 Convertor

EX-3 0011 1 Subtractor: Ex-3 to BCD Convertor

1001 BCD 1 Subtractor:9’s Complement of B

1010 BCD 1 Subtractor: 10’s Complement of B

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Conversion of Excess-3 to BCD(8421)

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BCD(8421) to Excess-3 Conversion

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Excess-3 to BCD Conversion

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K-Map Realization of the Input Over
Output

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 Block Diagram

Everyone need to verify

using the truth table of the
expressions after getting the
timing diagram or gtkwave
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 Binary to Gray Code Conversion

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Binary to Gray Code Conversion Circuit Diagram

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Binary to Gray Code Conversion….

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Binary to Gray Code Conversion….

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 Gray Code to Binary Conversion

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Gray Code to Binary Conversion Circuit Diagram

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Gray Code to Binary Conversion…

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Gray Code to Binary Conversion….

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 Binary Multiplier

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2-Bit Binary Multiplier

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2-Bit Binary Multiplier

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4-Bit by 4-Bit Multiplier

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 Magnitude Comparator

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Magnitude Comparator

 A magnitude comparator is a
combinational circuit that compares two
given numbers (A and B) and
determines whether one is equal to, less
than or greater than the other.

 The output is in the form of three binary

variables representing the conditions
A = B, A>B and A<B,
if A and B are the two numbers being
compared.

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 Realization of 2-Bit Magnitude Comparator
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
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Realization of 2-Bit Magnitude Comparator

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2-Bit Magnitude Comparator

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3 & 4 -Bits Magnitude Comparator

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 Multiplexer

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Multiplexer (Mux)-The Selector
• Digital multiplexer is a combinational logic
circuit that accepts many digital data and select
one of them (using selection lines) at any time
and pass it to the output.
• Multiplexer are also called as data selector
circuits or many to one circuit.
• Based on the selection line code one input is
selected and connected to output.
• In a MUX there are 2n inputs 1 output . So, in
general a MUX is represented as (2nx1), where,
n is the number of selection lines.
Multiplexer (Mux)
Designing of Multiplexers
Designing 2x1 Multiplexer
 To design 2x1 Multiplexer we must know the number of inputs, number of
selection lines required .
 2x1 means 21x1.
 Hence, it will have 2 inputs and 1 number of selection lines required. Let’s
take I0 and I1 be the inputs and S0 be the selection line.
S0 Output
I0 MUX
2x1 Y 0 I0 Y = SoIo+SoI1
I1

1 I1
S0
Designing 4x1 Multiplexer
Designing 8x1 Multiplexer
 To design 8x1 S2 S1 S0 Output
Multiplexer again we I0
I0
need number of inputs
I1
I2
MUX Y 0

0
0

0
0

1 I1
and number of selection .
.
8x1 0 1 0 I2
lines. 0 1 1 I3
I7
 8x1 means 2 x1, hence, it
3
S2 S1 S0
1 0 0 I4
I5
will have 8 inputs and 3 1 0 1

I6
selection lines.
1 1 0

1 1 1 I7

 Let’s take I0, I1, I2, I3, ……I7

be the inputs and S2 S1 S0 Y = S S S I +S S S I + S S S I +S S S I +
2 1 o o 2 1 o 1 2 1 o 2 2 1 o 1
be the selection lines. S2S1SoIo+S2S1SoI1 +S2S1SoIo+S2S1SoI1
Implementing 8x1 Multiplexer using Basic Gates
I0
I1
I2
MUX Y

.
.
8x1
I7
S2 S1 S0

Y = S2S1SoIo+S2S1SoI1+ S2S1SoI2+S2S1SoI3+
S2S1SoI4+S2S1SoI5 +S2S1SoI6+S2S1SoI7
Implementing Boolean functions using MUX
Problem:
Implement F(A,B,C,D) = ∑m(1,4, 5 , 7, 9, 12, 13) using 4 x 1 MUX

Procedure:
Step 1. Find out the MUX configuration to be Implemented
Step 2. Choose the Selection Lines out of the Input Variables
Step 3. Fill the Minterm/Maxterm into the K-Map and Simplify it to get the Truth Tables
values.

Step 4. Formulate the Output Expression (say Y)

Step 5. Substitute the Boolean Expression into Circuit Diagram
Procedure: F(A,B,C,D) = ∑m(1,4, 5 , 7, 9, 12, 13) using 4 x 1 MUX

• Step 1: Find out the MUX configuration to be Implemented

• Step 2: Choose the Selection Lines out of the Input Variables

• Given Inputs are F(A,B,C,D) = { A, B, C, D}, then
• Let Any two of the input variables are chosen as Select Lines(Say A and B)
Procedure: F(A,B,C,D) = ∑m(1,4, 5 , 7, 9, 12, 13) using 4 x 1 MUX
Implementing functions using Multiplexers
 Any given Logical expression can be implemented using Multiplexers, hence MUXs
are called as universal logic gates.

For example, full adder can be implemented using MUX

 For full adder circuit we have :

Sum = ∑m(1,2,4,7)
and Carry = ∑m(3,5,6,7)
It has three input, so can be implemented using 8x1 MUX.

 While implementing Boolean functions using MUX we just need to connect available
combinations (MUX input) to logic ‘1” and whichever combination is not present in
the expression must be connected to logc’0’.
Full adder implementation using MUX
I0
I1
I2
I3 MUX Sum = ∑m(1,2,4,7)
I4 8x1
I5 Sum = ABC+ABC+ABC+ABC
I6
I7
Logic
‘1’
A B C
Logic
‘0’
Full adder implementation using MUX
I0
I1
I2
I3 MUX Carry = ∑m(3,5,6,7)
I4 8x1
I5 Carry = ABC+ABC+ABC+ABC
I6
I7
Logic
‘1’
A B C
Logic
‘0’
MULTIPLEXERS TREE

 It is possible to expand the range of input for multiplexer beyond the available range in the
integrated circuits.

 This can be accomplished by interconnecting several multiplexers. For example two 8:1 mux
can be used together to form a 16:1 mux and two 16:1 mux can be used to realize the 32:1
mux.

 Even we can realize 32:1 mux can be realized with a smaller sized mux like 8:1 or 4:1 or 2:1 by
properly assigning the selection lines to those mux circuits.
16x1 Mux Using 8x1 Mux
Homework:

16x1 Mux Using 4x1 Mux

16x1 Mux Using 2x1 Mux

De-Multiplexer
• A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these
outputs. De-multiplexer is opposite to the multiplexer.
 1×2 De-Multiplexer
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e., S0, and single input, i.e.,
A. On the basis of the selection value, the input will be connected to one of the outputs. The block diagram and the truth
table of the 1×2 multiplexer are given below.
 1×4 De-Multiplexer
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection lines, i.e., S0 and
S1 and single input, i.e., A. On the basis of the combination of inputs which are present at the selection lines
S0 and S1, the input be connected to one of the outputs.
 1×8 De-Multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3 selection lines, i.e., S0,
S1and S2 and single input, i.e., A. On the basis of the combination of inputs which are present at the selection lines S 0, S1
and S2, the input will be connected to one of these outputs.
DMUX TREE: 1×8/1×16 DMUX Using 1×8 , 1×4 and 1×2 or DMUX, etc…
Implement Full Subtractor using De-Mux
Implement Full Subtractor using De-Mux
 Decoder: Code Converter
 Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines or

Multiple Input and Multiple Output Combinational Circuit. One of these outputs will be active
High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a
particular code. The outputs of the decoder are nothing but the min terms of ‘n’ input variables lines, when it
is enabled.
 A binary decoder is a digital circuit that converts a binary code into a set of outputs.

 Applications of decoders are converting

Binary to Other Codes like:

 Binary to Octal: 3 x8
 Binary to Hexadecimal: 4 x 16
 Binary to Decimal: 4 x 10
 2x4 Line Decoder
The 2-to-4-line binary decoder depicted above consists of an array of four AND gates. The 2 binary inputs labeled A and B
are decoded into one of 4 outputs, hence the description of a 2-to-4 binary decoder. Each output represents one of the
minterms of the 2 input variables, (each output = a minterm).
2x4 Line Decoder….
3 x 8 - Line Decoder
3 x 8 - Line Decoder….
Implement Full Adder using Decoder

S = Σ(1,2,4,7)
COUT = Σ (3, 5, 6, 7)
BCD to 7-segment Display Decoder
Test Cases: For Decimal Number = 0
The input lines for Zero are A = 0, B = 0, C = 0, and D = 0 and in the output lines, a to f are 1 and only g = 0. So, the g LED
display will not glow, and the rest of the LEDs will glow, and we get zero on display.
Test Cases: For Decimal Number = 2
The input lines for two are A = 0, B = 0, C = 1, and D = 0; in the output lines, a, b, d, e, and g are 1 and c and f are zero. So,
only a, b, d, e, and g will glow, and we get two on display.
 Encoders
 The combinational circuits that change the binary information into N output lines are
known as Encoders.
 The binary information is passed in the form of 2N input lines.
 The output lines define the N-bit code for the binary information. In simple words, the
Encoder performs the reverse operation of the Decoder.
 At a time, only one input line is activated for simplicity.
 The produced N-bit output code is equivalent to the binary information.

 Types of Encoders
There are different types of Encoders which are mentioned
below.
 4 to 2 Encoder
 Octal to Binary Encoder (8 to 3 Encoder)
 Decimal to BCD Encoder
4 x 2 Line Encoder
Octal to Binary Encoder (8 to 3 Encoder)
Octal to Binary Encoder (8 x 3 Encoder)….
Decimal to BCD Encoder
Decimal to BCD Encoder
Priority Encoder: 4 x 2 - Priority Encoder
A 4 to 2 priority encoder has 4 inputs: Y3, Y2, Y1 & Y0, and 2 outputs: A1 & A0. Here, the input, Y3 has the highest
priority, whereas the input, Y0 has the lowest priority. In this case, even if more than one input is ‘1’ at the same time, the
output will be the (binary) code corresponding to the input, which is having higher priority. The truth table for the priority
encoder is as follows.
Priority Encoder: 4 x 2 - Priority Encoder
 Continue……

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