+

William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 7
Input/Output
+
Generic
Model
of an I/O
Module
+
External Devices

 Provide a means of
 Three categories:
exchanging data between  Human readable
the external environment  Suitable for communicating with
and the computer the computer user
 Video display terminals (VDTs),
 Attach to the computer by a printers
link to an I/O module
 Machine readable
 The link is used to exchange
control, status, and data
 Suitable for communicating with
between the I/O module and equipment
the external device  Magnetic disk and tape systems,
sensors and actuators
 peripheral device  Communication
 An external device  Suitable for communicating with
connected to an I/O module remote devices such as a
terminal, a machine readable
device, or another computer
+
External
Device
Block
Diagram
+ Most common means of
computer/user interaction
Keyboard/Monitor User provides input through
the keyboard

International Reference The monitor displays data

provided by the computer
Alphabet (IRA)
A
 Basic unit of exchange is the Keyboard Codes
character
 Associated with each character is a code  When the user depresses a key it
 Each character in this code is generates an electronic signal that is
represented by a unique 7-bit binary interpreted by the transducer in the
code keyboard and translated into the bit
 128 different characters can be pattern of the corresponding IRA code
represented
 This bit pattern is transmitted to the
 Characters are of two types: I/O module in the computer
 Printable
 On output, IRA code characters are
 Alphabetic, numeric, and special
transmitted to an external device
characters that can be printed on
paper or displayed on a screen
from the I/O module
 Control  The transducer interprets the code
 Have to do with controlling the
and sends the required electronic
printing or displaying of characters signals to the output device either to
 Example is carriage return display the indicated character or
 Other control characters are perform the requested control
concerned with communications function
procedures
 I/O Modules Control and
timing
• Coordinates the

Module Function
flow of traffic
between internal
resources and
external devices

Processor
communicatio
Error detection n
• Detects and • Involves
reports command
transmission The major decoding, data,
errors status reporting,
functions for
address
an I/O recognition
module fall
into the
following
categories:

Device
Data buffering communicatio
• Performs the n
needed buffering
operation to • Involves
balance device commands,
and memory status
speeds information, and
data
I/O Module Structure
+
Programmed I/O
 Three techniques are possible for I/O operations:
 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the
I/O operation
 When the processor issues a command it must wait until the I/O
operation is complete
 If the processor is faster than the I/O module this is wasteful of
processor time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the
latter has completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly
without processor involvement
 Table 7.1
I/O Techniques

+
+
I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data
bus and subsequently transmit that data item to the
peripheral
 Three
Techniques
for Input of
a
Block of
Data
I/O Instructions
With programmed I/O there is a close correspondence between the I/O-
related instructions that the processor fetches from memory and the I/O
commands that the processor issues to an I/O module to execute the
instructions

Each I/O device connected through I/O modules is given

a unique identifier or address

The form of the

instruction
When the processor
issues an I/O Memory-mapped I/O
depends on the command, the
way in which command contains
external devices the address of the
are addressed desired device

Thus each I/O

module must There is a single address space for A single read line and a single write
interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for
itself
+
I/O Mapping Summary

 Memory mapped I/O

 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available

 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set
 Memory
Mapped
I/O

Isolated
I/O

+
Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O
module to be ready for either reception or
transmission of data

An alternative is for the processor to issue an

I/O command to a module and then go on to do
some other useful work

The I/O module will then interrupt the processor

to request service when it is ready to exchange
data with the processor

The processor executes the data transfer and

resumes its former processing
+

Simple Interrupt
Processing
+
Changes
in Memory
and Registers
for an
Interrupt
Design Issues

• Because there
will be multiple
I/O modules how
does the
Two design processor
determine which
issues arise device issued
in the interrupt?
implementin • If multiple
g interrupt interrupts have
I/O: occurred how
does the
processor decide
which one to
process?
+
Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have
multiple I/O modules attached to it
 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose
job is to poll each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate
device-service routine, avoiding the need to execute a general interrupt-service
routine first
 Bus arbitration (vectored)
 An I/O module must first gain control of the bus before it can raise the interrupt
request line
 When the processor detects the interrupt it responds on the interrupt acknowledge
line
+

Intel
82C59A
Interrupt
Controller
+ Intel 82C55A
Programmable Peripheral Interface
+
Keyboard/
Display
Interfaces to
82C55A
Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent

drawbacks:

1) The I/O transfer rate is limited by the

speed with which the processor can test
and service a device

2) The processor is tied up in managing an

I/O transfer; a number of instructions
must be executed for each I/O transfer

+
 When large volumes of data are to be moved a
more efficient technique is direct memory access
(DMA)
+
Typical DMA
Module Diagram
 DMA

DMA

+
DMA Operation
+
Alternative
DMA
Configurations
8237 DMA Usage of System Bus
+
Fly-By DMA Controller

Data does not 8237 contains four

pass through and DMA channels
is not stored in • Programmed
DMA chip independently
Can do memory to
• DMA only memory via • Any one active
between I/O port register • Numbered 0, 1,
and memory 2, and 3
• Not between two
I/O ports or two
memory
locations
 Table 7.2
Intel
8237A
Registers

E/D =
enable/disable
+
Evolution of the I/O Function

1. The CPU directly controls

4. The I/O module is given direct
a peripheral device.
access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving the
is added. The CPU uses CPU, except at the beginning and
programmed I/O without end of the transfer.
interrupts.
5. The I/O module is enhanced to
3. Same configuration as in become a processor in its own
step 2 is used, but now right, with a specialized instruction
interrupts are employed. set tailored for I/O
The CPU need not spend
6. The I/O module has a local memory
time waiting for an I/O
of its own and is, in fact, a
operation to be
computer in its own right. With
performed, thus
this architecture a large set of I/O
increasing efficiency.
devices can be controlled with
minimal CPU involvement.
+
I/O
Channel
Architecture
+
Parallel
and
Serial
I/O
Point-to-Point and Multipoint
Configurations
Multipoint external
interfaces are used to
Connection between an I/O Point-to-point interface
support external mass
module in a computer provides a dedicated line
storage devices (disk and
system and external between the I/O module
tape drives) and multimedia
devices can be either: and the external device
devices (CD-ROMs, video,
audio)

On small systems
(PCs, workstations)
typical point-to-point Are in effect external
point-to-point
links include those to buses
the keyboard, printer,
and external modem

Example is EIA-232
multiport
specification
+
Thunderbolt

 Provides up to 10 Gbps throughput

 Most recent and fastest in each direction and up to 10
Watts of power to connected
peripheral connection
peripherals
technology to become
available for general-  A Thunderbolt-compatible
purpose use peripheral interface is considerably
more complex than a simple USB
device
 Developed by Intel with
collaboration from Apple  First generation products are
primarily aimed at the
 The technology combines professional-consumer market
data, video, audio, and such as audiovisual editors who
power into a single high- want to be able to move large
volumes of data quickly between
speed connection for
storage devices and laptops
peripherals such as hard
drives, RAID arrays, video-  Thunderbolt is a standard feature
capture boxes, and network of Apple’s MacBook Pro laptop and
interfaces iMac desktop computers
+

Computer Configuration with Thunderbolt

+
Thunderbolt
Protocol
Layers
+
InfiniBand

 Recent I/O specification aimed at the high-end server market

 First version was released in early 2001
 Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
 Has become a popular interface for storage area networking
and other large storage configurations
 Enables servers, remote storage, and other network devices
to be attached in a central fabric of switches and links
 The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices
InfiniBand Switch Fabric
+
InfiniBand Operation

 Each physical link between  The InfiniBand switch maps

a switch and an attached traffic from an incoming
interface can support up to lane to an outgoing lane to
16 logical channels, called route the data between the
virtual lanes desired end points
 One lane is reserved for
fabric management and  A layered protocol
the other lanes for data architecture is used,
transport consisting of four layers:
 Physical
 A virtual lane is temporarily
dedicated to the transfer of
 Link
data from one end node to  Network
another over the InfiniBand  Transport
fabric
+
Table 7.3
InfiniBand Links and Data
Throughput Rates
InfiniBand Communication Protocol
Stack
+
zEnterprise 196
 Introduced in 2010
 IBM’s latest mainframe computer offering
 System is based on the use of the z196 chip
 5.2 GHz multi-core chip with four cores
 Can have a maximum of 24 processor chips (96 cores)

 Has a dedicated I/O subsystem that manages all I/O operations

 Of the 96 core processors, up to 4 of these can be dedicated for I/O
use, creating 4 channel subsystems (CSS)
 Each CSS is made up of the following elements:
 System assist processor (SAP)
 Hardware system area (HSA)
 Logical partitions
 Subchannels
 Channel path
 Channel
I/O System Organization
IBM z196 I/O System Structure
+ Summary
Input/Output
Chapter 7
 Direct memory access
 External devices
 Drawbacks of programmed and
interrupt-driven I/O
 Keyboard/monitor  DMA function
 Disk drive  Intel 8237A DMA controller
 I/O modules
 Module function  I/O channels and processors
 I/O module structure  The evolution of the I/O function
 Programmed I/O  Characteristics of I/O channels
 Overview of programmed I/O
 I/O commands
 The external interface
 Types of interfaces
 I/O instructions
 Point-to-point and multipoint
 Interrupt-driven I/O configurations
 Interrupt processing  Thunderbolt
 Design issues  InfiniBand
 Intel 82C59A interrupt controller
 Intel 82C55A programmable
 IBM zEnterprise 196 I/O