William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 7
Input / Output
On computer system overview’s
• Computer System
• Computer Function
• Basic Computer Components
• Computer Function Reviewed
• Instruction Cycle
• Instruction Cycle with Interrupts
• Interconnections Structures
• Buses
Input / Output
• The computer system’s I/O architecture is
its interface to the outside world.
• This architecture is designed to provide a
systematic means of
—controlling interaction with the outside world and
—to provide the operating system with the
information it needs to manage I/O activity
effectively.
• Input or output devices attached to the
computer are also called peripherals.
• Among the most common peripherals are
keyboards, display units, and printers.
Peripheral
input Device
• Keyboard
• Optical input devices
— Card Reader
— Paper Tape Reader
— Optical Character Recognition (OCR)
— Optical Bar code reader (OBR)
— Digitizer
— Optical Mark Reader
• Magnetic Input Devices
— Magnetic Stripe Reader
— Magnetic Ink Character Recognition (MICR)
• Screen Input Devices
— Touch Screen
— Light Pen
— Mouse
• Analog Input Devices
Peripheral
Output Device
• Card Puncher, Paper Tape Puncher
• Monitor (CRT, LCD, LED)
• Printer (Impact, Ink Jet, Laser, Dot Matrix)
• Analog
• Voice
Input/output Problems
• Wide variety of peripherals
—Delivering different amounts of data
—At different speeds
—In different formats
• All slower than CPU and RAM
• So it Need I/O modules
Purpose Input/output Module
• I/O modules interface to the system bus or
central switch (CPU and Memory), interfaces
and controls to one or more peripheral devices.
• I/O operations are accomplished through a wide
assortment of external devices that provide a
means of exchanging data between external
environment and computer by a link to an I/O
module.
• The link is used to exchange control status and
data between I/O module and the external
devices.
• Interface to the processor and memory via the
system bus or control switch
• Interface to one or more peripheral devices
Generic Model of I/O Module
Peripherals
• Peripherals are not directly connected to the system bus
instead an I/O module is used which contains logic for
performing a communication between the peripherals and the
system bus. The reasons due to which peripherals do not
directly connected to the system bus are:
• There are a wide variety of peripherals each with varying
methods of operation.
— Impractical to for the processor to accommodate all.
• Data transfer rates are often slower than the processor and/or
memory.
— Impractical to use the high-speed system bus to
communicate directly.
• Data transfer rates may be faster than that of the processor
and/or memory.
— This mismatch may lead to inefficiencies if improperly
managed.
— Thus, it is impractical to use high speed system bus to
External Devices
 Human readable
—Screen, printer, keyboard
 Machine readable
Disks, tapes
—Functional view of disks as part of memory
hierarchy
—Structurally part of I/O system
Sensors, actuators
Monitoring and control
 Communication
—Modem
—Network Interface Card (NIC)
—
External Device Block Diagram
The External Device – I/O
Module
• Control signals: determine
the function that will be
performed
• Data: set of bits to be sent of
received
• Status signals: indicate the
state of the device
• Control logic: controls the
device’s operations
• Transducer: converts data
from electrical to other forms of
energy
• Buffer: temporarily holds
data being transferred
I/O Module Function
• Control & Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection
Control & Timing:
Control & Timing: I/O module includes control and
timing to coordinate the flow of traffic between
internal resources and external devices. The control of
the transfer of data from external devices to
processor consists following steps:
 The processor interrogates the I/O module to check
status of the attached or external device.
 The I/O module returns the device status.
 If the device is operational and ready to transmit, the
processor requests the transfer of data by means of a
command to I/O module.
 The I/O module obtains the unit of data from the
external device.
 The data are transferred from the I/O module to the
processor
Processor Communication :
Processor communication involves:
 Command decoding:
 Commands sent as signals on control bus
 I/O module accepts commands from the processor.
E.g. disk: Read Sector, Write Sector, Seek, …
 Data: Data are exchanged between the processor and I/O
module over the bus.
 Status reporting
 Peripherals are very slow compared to processor
 May take some time after a READ command before data
is ready
 Typical signals: BUSY, READY
 Address decoding –
 Module recognizes unique address for each device it
controls
Device Communication :
 On the other side the I/O module has to communicate with
the device
 Commands
 Status information
 Data
 Buffering is often essential
 Data Buffering: I/O module must be able to operate at both
device and memory speeds.
 If the I/O device operates at a rate higher than the memory access
rate, then the I/O module performs data buffering.
 If I/O devices rate slower than memory, it buffers data so as not to
tie up the memory in slower transfer operation.
 Handles the speed mismatch between memory and the
device
 Low speed devices need to have data from memory
buffered
 High speed devices need to have data going to memory
buffered
Error Detection and Reporting :
 Mechanical and Electrical malfunction
 Ex. Out of paper, paper jam, bad disk sector
 Data communication errors
 Typically detected with parity bits: It is an extra bit
added to a binary code to ensure the accuracy of
data transmission or storage.
I/O Steps
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
• Variations for output, DMA, etc.
I/O Module Diagram
I/O Module Diagram
• • Module connects to the
computer through a set of
signal lines – system bus
• • Data transferred to and
from the module are buffered
with data registers
• • Status provided through
status registers – may also
act as control registers
• • Module logic interacts
with processor via a set of
control signal lines
• • Processor uses control
signal lines to issue
commands to the I/O module
• • Module must recognize
and generate addresses for
devices it controls
I/O Module Decisions
• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for
CPU
• Also O/S decisions
—e.g. Unix treats everything it can as a file
Input Output Techniques
 There are three principal I/O techniques:
• programmed I/O, in which I/O occurs under the
direct and continuous control of the program
requesting the I/O operation;
• interrupt-driven I/O, in which a program issues an
I/O command and then continues to execute, until
it is interrupted by the I/O hardware to signal the
end of the I/O operations; and
• direct memory access (DMA), in which a
specialized I/O processor takes over control
of an I/O operation to move a large block of
data.
Three Techniques for
Input of a Block of Data
1. Programmed I/O
• CPU has direct control over I/O
—Sensing status
—Read/write commands
—Transferring data
• CPU waits for I/O module to complete
operation
• Wastes CPU time
Programmed I/O - detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
I/O Commands
• CPU issues address
—Identifies module (& device if >1 per module)
• CPU issues command
—Control - activate a peripheral and telling
module what to do
– e.g. spin up disk
—Test - check status: test various status conditions
associated with an I/O module and its
peripherals
– e.g. power? Error?
—Read/Write
– Module transfers data via buffer from/to device
Addressing I/O Devices
• Under programmed I/O data transfer is
very like memory access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier
(address)
I/O Mapping
• Memory mapped I/O
— A single set of read/write control lines (no distinction
between memory and I/O transfer)
— Memory and I/O addresses share the common
address space which reduces memory address range
available
— No specific input or output instruction so the same
memory reference instructions can be used for I/O
transfers
— Considerable flexibility in handling I/O operations
• Isolated I/O
— Separate I/O read/ write control lines in addition to
memory read/write control lines
— Separate (isolated) memory and I/O address spaces
— Distinct input and output instructions
— Special commands for I/O
–
2. Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral
whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
Simple Interrupt
Processing
CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each
instruction cycle
• If interrupted:-
—Save context (registers)
—Process interrupt
– Fetch data & store
Design Issues
• How do you identify the module issuing
the interrupt? Read it!!!
• How do you deal with multiple interrupts?
Read it!!!
—i.e. an interrupt handler being interrupted
Identifying Interrupting Module (1)
• Different line for each module
—PC
—Limits number of devices
• Software poll
—CPU asks each module in turn
—Slow
Identifying Interrupting Module (2)
• Daisy Chain or Hardware poll
—Interrupt Acknowledge sent down a chain
—Module responsible places vector on bus
—CPU uses vector to identify handler routine
• Bus Master
—Module must claim the bus before it can raise
interrupt
—e.g. PCI & SCSI
Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower
priority lines
• If bus mastering only current master can
interrupt
3. Direct Memory Access
• Interrupt driven and programmed I/O
require active CPU intervention
—Transfer rate is limited
—CPU is tied up
• DMA is the answer
DMA Function
• Additional Module (hardware) on bus
• DMA controller takes over from CPU for
I/O
Typical DMA Module Diagram
DMA Operation
• CPU tells DMA controller:-
—Read/Write
—Device address
—Starting address of memory block for data
—Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when
finished
DMA Transfer Cycle Stealing
• DMA controller takes over bus for a
cycle
• Transfer of one word of data
• Not an interrupt
—CPU does not switch context
• CPU suspended just before it accesses
bus
—i.e. before an operand or data fetch or a data
write
• Slows down CPU but not as much as CPU
doing transfer
Q?
Which one is best techniques among the
three techniques?
• DMA (Direct Memory Access) controllers can
typically move data from and to memory with
either I/O or memory.
• Since it operates independently of the CPU,
the CPU does not need to manage the process
with each transfer.
• If you are transferring multiple pieces of data, it
can be faster using the DMA controller.
Q?
Why is DMA – based I/O better than I/O
techniques?
• This technique overcomes the drawbacks of
other two I/O techniques which are the time
consuming process when issuing command for
data transfer and tie-up the processor in data
transfer while the data processing is neglected.
• It is more efficient to use DMA method when
large volume of data has to be transferred.
DMA and Interrupt Breakpoints During an
Instruction Cycle
Aside
• What effect does caching memory have
on DMA?
• What about on board cache?
• Hint: how much are the system buses
available?
DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
—I/O to DMA then DMA to memory
• CPU is suspended twice
DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses system bus once
—DMA to memory
• CPU is suspended once
DMA Configurations (3)

• Separate I/O Bus

• System Bus supports all DMA enabled
devices
• Each transfer uses System Bus once
—DMA to memory
•
Reading
• How do you identify the module issuing
the interrupt? Read it!!!
• How do you deal with multiple interrupts?
Read it!!!
—i.e. an interrupt handler being interrupted
• What effect does caching memory have
on DMA?
• What about on board cache?
• Hint: how much are the system buses
available?
• What are DMA enable devices???
END