COMBINATIONAL

LOGIC

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Combinational vs. Sequential
Logic

In Out
Logic Logic
In Out
Circuit Circuit

State

(a) Combinational (b) Sequential

Output = f(In ) Output = f(In, Previous In)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Static CMOS Circuit

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Static CMOS
VDD

In1
In2 PUN PMOS Only
In3

F=G

In1
In2 PDN NMOS Only
In3

VSS

PUN and PDN are Dual Networks

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 NMOS Transistors in Series/Parallel
Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 PMOS Transistors in Series/Parallel
Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Complementary CMOS Logic Style Construction
(cont.)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Example Gate: NAND

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Example Gate: NOR

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Example Gate: COMPLEX CMOS
GATE

VDD

B
A
C

D
OUT = D + A• (B+C)
A
D
B C

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 4-input NAND Gate

Vdd
VDD
VDD
In1 In2 In3 In4
Out
In1

In2

Out Out In3

In4
GND
In1 In2 In3 In4
GND

In1 In2 In3 In4

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Standard Cell Layout
Methodology

metal1 VDD

Well

VSS
Routing Channel
signals
polysilicon

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Two Versions of (a+b).c

VDD VDD

x
x

GND GND

a c b a b c

(a) Input order {a c b} (b) Input order {a b c}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Logic Graph

VDD
x
b PUN
j c c
a x i VDD

x
b j a
c
i PDN
GND
a b

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Consistent Euler Path

x i VDD

b a
j

GND

{ a b c}
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Example: x = ab+cd
x x

b c b c

x VDD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VD D

GND
a b c d
(c) stick diagram for ordering {a b c d}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Properties of Complementary CMOS
Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Transistor Sizing
• for symmetrical response (dc, ac)
• for performance

VDD

B 12
A 6
Input Dependent
C 12
Focus on worst-case
D 6
F
A 2
D 1
B 2 C 2

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Propagation Delay Analysis - The Switch
Model
RON
=

VDD VDD
VDD
Rp Rp Rp
Rp
A B B
A F
Rn Rp
F CL
B A
Rn
CL F
Rn Rn Rn
A CL
A B
A

(a) Inverter (b) 2-input NAND (c) 2-input NOR

tp = 0.69 Ron CL

(assuming that CL dominates!)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 What is the Value of Ron?

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Numerical Examples of Resistances for
1.2m CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Analysis of Propagation Delay
VDD 1. Assume Rn =Rp = resistance of minimum
Rp Rp sized NMOS inverter

A B 2. Determine “Worst Case Input” transition

F (Delay depends on input values)
Rn
CL 3. Example: tpLH for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
tpLH = 0.69Rp CL
2-input NAND 4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Design for Worst Case
V DD
VDD

1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2

Here it is assumed that Rp = Rn

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Influence of Fan-In and Fan-Out
on Delay
VDD

A B C D Fan-Out: Number of Gates Connected

2 Gate Capacitances per Fan-Out

A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
D 2. Capacitance Increasing
(tpHL )

t = a FI + a FI 2 + a FO
p 1 2 3

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 tp as a function of Fan-In

4.0

tpHL
3.0
tp (nsec)

2.0 quadratic tp

1.0
tpLH
linear

0.0
1 3 5 7 9
fan-in

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Fast Complex Gate - Design
Techniques
• Transistor Sizing:
As long as Fan-out Capacitance dominates

• Progressive Sizing:
Out
InN MN CL
M1 > M2 > M3 > MN
In3 M3 C3
Distributed RC-line
In2 M2 C2

In1 M1 C1
Can Reduce Delay with more than 30%!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Fast Complex Gate - Design
Techniques (2)
• Transistor Ordering

critical path critical path

CL CL
In3 M3 In1 M1

In2 M2 C2 C2
In2 M2

In1 M1 C1 C3
In3 M3

(a) (b)
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Fast Complex Gate - Design
Techniques (3)

• Improved Logic Design

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Fast Complex Gate - Design
Techniques (4)

• Buffering: Isolate Fan-in from Fan-out

CL CL

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Example: Full Adder

VDD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A

Co B

Co = AB + C i(A+B)

28 transistors
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 A Revised Adder Circuit

V DD

VDD V DD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate
Generate
A B B A B Ci A

24 transistors

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Ratioed Logic

VDD

• N transistors + Load
Resistive
• VOH = V DD
Load RL

• VOL = RPN

F RPN + RL

In1 • Assymetrical response

In2 PDN
In3 • Static power consumption

• tpL= 0.69 RLCL

VSS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Active Loads

VDD VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Load Lines of Ratioed Gates

1
Current source

0.75
IL(Normalized)

Pseudo-NMOS
0.5

Depletion load
0.25
Resistive load

0
0.0 1.0 2.0 3.0 4.0 5.0
Vout (V)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Pseudo-NMOS

VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

 V OL 2  kp 2
k n  VDD – V Tn V OL – -------------  = ------ V DD – VTp 
 
 2  2

kp
V OL =  VDD – V T  1 – 1 – ------ (assuming that V T = V Tn = VTp )
kn

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Pseudo-NMOS NAND Gate

VDD

GND

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Improved Loads

VDD

M1 M1 >> M2
Enable M2

CL
A B C D

Adaptive Load

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Improved Loads (2)

VDD VDD

M1 M2

Out Out

A
A
PDN1 PDN2
B
B

VSS VSS

Dual Cascode Voltage Switch Logic (DCVSL)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Example

Out

Out

B B B B

A A

XOR-NXOR gate

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Pass-Transistor Logic

Switch Out A
Out
Inputs

Network B
B

• N transistors
• No static consumption

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 NMOS-only switch

C=5V C=5V
M2
A=5V A=5V B
Mn
B
CL M1

VB does not pull up to 5V, but 5V - VTN

Threshold voltage loss causes

static power consumption

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Solution 1: Transmission Gate

C
C

A B A B

C
C

C=5V
A=5V
B
CL
C=0V

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Resistance of Transmission Gate

30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
20000.0
R (Ohm)

Rp

10000.0
Req

0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vout

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Pass-Transistor Based Multiplexer

S S
VDD

VDD
S

A
M2

S F

M1
B

GND
In S S In
1 2

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Transmission Gate XOR

B
M2

A
A
F
M1 M3/M4
B

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Delay in Transmission Gate
Networks

5 5 5 5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In

C C C C C
0 0 0 0

(a)

Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In

C C C C C

(b)
m

Req Req Req Req Req Req

In
C CC C C CC C

(c)
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Elmore Delay (Chapter 8)

Vin R1 1 R2 2 Ri-1 i-1 Ri i RN N

C1 C2 Ci-1 Ci CN

Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin

N N N i
 =  R  C =  C  R
N i j i j
i=1 j=i i=1 j=1

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Delay Optimization

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 (2) NMOS Only Logic: Level Restoring
Transistor

VDD
Level Restorer VDD
Mr
B
M2
X
A Mn Out
M1

• Advantage: Full Swing

• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Level Restoring Transistor

5.0 with
5.0
without
Vout (V)

3.0 3.0 without

with

VX
VB
1.0 1.0

-1.00 2 4 6 -1.00 2 4 6
t (nsec) t (nsec)
(a) Output node (b) Intermediate node X

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Solution 3: Single Transistor Pass Gate
with VT=0

VDD

VDD
0V 5V

VDD 0V Out

5V

WATCH OUT FOR LEAKAGE CURRENTS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Complimentary Pass Transistor Logic

A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network

B B B B B B

A A A

B F=AB B F=A+B A F=AÝ

A A A
(b)

B F=AB B F=A+B A F=AÝ

AND/NAND OR/NOR EXOR/NEXOR

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 4 Input NAND in CPL

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Dynamic Logic
VDD VDD

 Mp  Me
Out

In1
CL
In1 In2 PUN
In2 PDN In3
In3 Out

 Me  Mp CL

n network  p network

• Precharge
2 phase operation:
• Evaluation
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Example
VDD

 Mp
• N + 1 Transistors
Out
• Ratioless

• No Static Power Consumption

A • Noise Margins small (NML)
C
• Requires Clock
B

 Me

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Transient Response
6.0
 Vout

4.0
EVALUATION PRECHARGE
Vout (Volt)

2.0

0.0
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Dynamic 4 Input NAND Gate

VDD

Out

In1
In2
In3
In4

 GND

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Reliability Problems —
Charge Leakage
VDD

 Mp
Out
(1) CL
A t
Vout precharge evaluate
(2)

 Me

t
(a) Leakage sources (b) Effect on waveforms

Minimum Clock Frequency: > 1 MHz

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Charge Sharing
(redistribution)
VDD case 1) if V out < VTn

 Mp C V = C V t  + C  V V V 
L DD L out a DD – Tn X
Out
or
CL Ca
V   - V DD – V Tn V X 
A Ma out = Vout t – V DD = – -------
CL
X

Ca
B=0 Mb case 2) if V out > VTn

 Ca 
Cb V  ---------------------- 
 Me out = –V DD  C + C 
a L

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Charge Redistribution -
Solutions
VDD VDD

Mbl  Mp Mbl 
 Mp
Out
Out
A Ma A Ma

B Mb B Mb

  Me
Me

(a) Static bleeder (b) Precharge of internal nodes

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Clock Feedthrough
VDD

 Mp could potentially forward

bias the diode
Out

CL 5V
A Ma 
X

Ca
B Mb overshoot

Cb out
 Me

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Clock Feedthrough and Charge
Sharing

output without redistribution (Ma off)

6
feedthrough

out
4 
V (Volt)

internal node in PDN

0
0 1 2 3
t (nsec)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Cascading Dynamic Gates
VDD VDD V


 Mp  Mp
In
Out1 Out2

Out1
In VTn

Out2 V
 Me  Me t

(a) (b)

Only 0 1 Transitions allowed at inputs!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Domino Logic

VDD VDD
VDD
 Mp  Mp
Mr
Out1

Out2
In1 Static Inverter
In2 PDN In4 PDN with Level Restorer
In3

 Me  Me

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 Domino Logic -
Characteristics

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter
move VM upwards by increasing PMOS

• Adding level restorer reduces leakage and

charge redistribution problems

• Optimize inverter for fan-out

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 np-CMOS

VDD VDD

 Mp  Me
Out1

In1 PUN
In2 PDN In4
In3 Out2

 Me  Mp

Only 1 0 transitions allowed at inputs of PUN

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 np CMOS Adder

VD D VD D
VDD VDD
 
  S1
Ci1
A1 B1 B1 A1
B1 Ci1 A1
A1
 B1
  Ci2


VDD
VDD
VDD 


A0 Ci1 B0
A0 B0 Ci0 A0
A0 B0 B0 Ci0
  S0

Ci0
Carry Path
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
 Manchester Carry Chain Adder
VDD
Total Area:
225 m 48.6 m
 0.5
P0 P1 P2 P3 P4
M0 M1 M2 M3 M4
3 2.5 2 1.5 1
Ci,0 1.5 Co,4
3.5 3 2.5 2 1
G0 G1 G2 G3 G4

 4 3.5 3 2.5 2
1.5

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

 CMOS Circuit Styles - Summary

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995