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Commits on Jan 19, 2022

• nexus: Fix BB sim model

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Commits on Jan 4, 2022

• manual: Fix cell-stmt order

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Commits on Jul 6, 2021

• ecp5: Add DCSC blackbox

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Commits on Jun 16, 2021

• pyosys: Clear SIGINT handler after Python loads

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Commits on Jun 11, 2021

• opt_muxtree: Update port_off and port_idx even for constant bits

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Commits on May 15, 2021

• intel_alm: Fix illegal carry chains

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• intel_alm: Add global buffer insertion

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• intel_alm: Add IO buffer insertion

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Commits on Mar 17, 2021

• Blackbox all whiteboxes after synthesis

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• blackbox: Include whiteboxed modules

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Commits on Feb 12, 2021

• Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct

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Commits on Jan 23, 2021

• dpi: Support for chandle type

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Commits on Dec 8, 2020

• nexus: Add MULTADDSUB9X9WIDE sim model

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Commits on Dec 7, 2020

• nexus: Add LRAM inference

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Commits on Dec 2, 2020

• Merge pull request #2467 from YosysHQ/dave/nexus-carry-fix

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• nexus: More efficient CO mapping

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Commits on Nov 20, 2020

• nexus: DSP inference support

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Commits on Nov 18, 2020

• nexus: Add DSP simulation model

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Commits on Oct 22, 2020

• nexus: Add make_transp to BRAMs

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Commits on Oct 15, 2020

• synth_nexus: Initial implementation

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Commits on Oct 1, 2020

• Update .gitignore

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Commits on May 12, 2020

• ecp5: Add missing SERDES parameters

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Commits on Apr 25, 2020

• cxxrtl: Round up constant width

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Commits on Apr 21, 2020

• sim: Fix handling of constant-connected cell inputs at startup

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Commits on Apr 17, 2020

• qbfsat: Fix illegal use of 'stdout' identifier

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Commits on Apr 16, 2020

• ecp5: Force SIGNED ports to be 1 bit

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• Merge pull request #1943 from YosysHQ/dave/fix-1919

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• ast: Fix handling of identifiers in the global scope

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Commits on Apr 15, 2020

• Merge pull request #1897 from YosysHQ/dave/bram-rejection-fix

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Commits on Apr 14, 2020

• cxxrtl: Fix handling of unclocked memory read ports

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Commits on Apr 12, 2020

• Merge pull request #1907 from YosysHQ/dave/fix-1906

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• verilog: Fix write to deleted object

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Commits on Apr 10, 2020

• memory_bram: Fix ignorance of valid, matched rules

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Commits on Apr 1, 2020

• Merge pull request #1844 from YosysHQ/dave/gen-source-loc

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• verilog: Add location info for generate constructs

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