Multibit Adder Architecture Failure

[shrekliao]

Hi VTR Team,
I'm encountering issues running multibit adder architectures with existing simple benchmarks in VTR8.

Steps to Reproduce:
Specifically, I've attempted to use the following architectures and benchmarks:
Architectures:
k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
Benchmarks:
Sum8.v

Current Behaviour
VPR fails with the following error:

Message in GDB:

.blif netlist file is missing outputs:

On the other hand, when running existing Spree.v benchmark, VPR fails with the following error:
/mnt/vault0/cliao43/vtr_cc/vtr-verilog-to-routing/vpr/src/timing/PreClusterDelayCalculator.h:127
prim_comb_delay: Assertion 'time.valid()' failed (Found no primitive combinational delay for edge).

My Environment:
VTR revision used: Master branch of github repo
Operating System and version: Ubuntu 22.04.4 LTS

I'm wondering if anyone else has encountered similar issues or if there are known workarounds for this problem. Any insights or suggestions would be greatly appreciated.