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Insights: verilog-to-routing/vtr-verilog-to-routing
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11 Pull requests merged by 5 people
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[CI] Added Test Suite Verification to CI
#3121 merged
Jun 10, 2025 -
Removed duplicate items in GUI
#3116 merged
Jun 9, 2025 -
vpr command line doc: add --read_initial_place_file and clarify file formats for place options
#3119 merged
Jun 6, 2025 -
[VPR][Utils] Add helper function to get RRNodeId from AtomPinId
#3113 merged
Jun 6, 2025 -
[AP] Optimized Primitive Vector Class
#3106 merged
Jun 6, 2025 -
Update golden results
#3115 merged
Jun 5, 2025 -
[CI] Added Quick Titanium S10 Tests
#3104 merged
Jun 4, 2025 -
[STA] Updated Tutorial
#3103 merged
Jun 4, 2025 -
[Place] Expand search range for sparse blocks
#2960 merged
Jun 4, 2025 -
Improve comments in Makefile
#3097 merged
Jun 3, 2025 -
[Infra] Converted Pin to Pin Annotations into Vector
#3101 merged
Jun 3, 2025
9 Pull requests opened by 5 people
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[WIP] System Verilog Testing #3
#3114 opened
Jun 5, 2025 -
[VPR][Pack] Breaking Ties When Placing Primitives
#3118 opened
Jun 6, 2025 -
Add Xilinx arch tests to CI
#3120 opened
Jun 6, 2025 -
[AP][Legalization] Updated the Mass Abstraction
#3123 opened
Jun 8, 2025 -
Update ezgl to use submodules
#3124 opened
Jun 9, 2025 -
Read/Write Encrypted XML Files
#3125 opened
Jun 9, 2025 -
Update OpenFPGA
#3126 opened
Jun 9, 2025 -
[Build] Resolved Most IPO Warnings
#3127 opened
Jun 10, 2025 -
[CI] Revived Simple Missing Strong Tests
#3128 opened
Jun 10, 2025
41 Issues closed by 5 people
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"Crit Path Routing" and "Crit Path Routing Delays" items are doubled
#2407 closed
Jun 9, 2025 -
CI failures due to old library versions
#2356 closed
Jun 9, 2025 -
Can't write out large rr_graphs in capnp format
#2352 closed
Jun 9, 2025 -
Ability to search & highlight resources using the graphics_commands
#2350 closed
Jun 9, 2025 -
About the suspected anomaly in power estimation
#2318 closed
Jun 8, 2025 -
can't pack adder
#2308 closed
Jun 8, 2025 -
Small code improvement with NO_GRAPHICS
#2300 closed
Jun 8, 2025 -
NightlyTestManual May 25 Run Failures
#3091 closed
Jun 7, 2025 -
commands for the shortes place and route
#2260 closed
Jun 7, 2025 -
Document some missing vpr command line options
#2198 closed
Jun 6, 2025 -
Xilinx BRAM future features
#2250 closed
Jun 6, 2025 -
VPR failed when running with the architecture description file that comes with VTR in COFFE_22nm
#2248 closed
Jun 6, 2025 -
Can the project be compiled and run in the windows environment?
#2245 closed
Jun 6, 2025 -
Why can't I use the “ --disp on ” option？
#2244 closed
Jun 6, 2025 -
The congestion heat map is invisiable
#2242 closed
Jun 6, 2025 -
how to generate a 130nm tech xml file
#2241 closed
Jun 6, 2025 -
Float precision issue when reading rr_graph
#2240 closed
Jun 6, 2025 -
NoC Failed to find architecture file
#2229 closed
Jun 6, 2025 -
Hard and Soft Logic Mixing for Adders
#2216 closed
Jun 6, 2025 -
Why place and route results are the same every time?
#2201 closed
Jun 5, 2025 -
aes_core and des doesn't go through ODIN_II!
#2192 closed
Jun 5, 2025 -
spree.v doesn't go through ODIN
#2191 closed
Jun 5, 2025 -
No difference in .route file no matter chosing route_type as detailed or global
#2184 closed
Jun 5, 2025 -
Support falling edge clocks (for FFs and timing analysis)
#2182 closed
Jun 5, 2025 -
--fix_pins file.pads
#2176 closed
Jun 5, 2025 -
FPGA Fabric Architecture
#2174 closed
Jun 5, 2025 -
[Place] Unnecessary microoptimization in override_delay_model
#3049 closed
Jun 4, 2025 -
Expand y_range Search for ymax
#2959 closed
Jun 3, 2025 -
how to use the routing resource map?
#2162 closed
Jun 3, 2025 -
packing procedure research
#2156 closed
Jun 3, 2025 -
Is there any example about the basic usage of re_cluster methods?
#2155 closed
Jun 3, 2025 -
Error executing run_vtr_flow with -start yosys
#2152 closed
Jun 3, 2025 -
Improving automatic sizing algorithm
#2149 closed
Jun 3, 2025 -
Documentation has deprecated information on VTR pre-synthetized benchmark
#2142 closed
Jun 3, 2025 -
Unable to route ISPD benchmarks using VPR
#2140 closed
Jun 3, 2025 -
Difference in behavioral memory inference between ODIN and ODIN+Yosys
#2131 closed
Jun 3, 2025 -
VPR Pack: C-style Arrays to C++ Vectors
#2087 closed
Jun 3, 2025 -
Assertion 'clk_pin' failed
#2075 closed
Jun 3, 2025
6 Issues opened by 4 people
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Portable VTR Release with a Static Build of VTR
#3122 opened
Jun 8, 2025 -
[TestCoverage] Failing VTR Benchmarks on the 7Series Architecture
#3117 opened
Jun 6, 2025 -
[GUI] Floating triangles drawn when primitive nets enabled.
#3109 opened
Jun 4, 2025 -
Embed slang-yosys plugin as a SystemVerilog frontend for yosys
#3108 opened
Jun 4, 2025 -
[TestCoverage] Failing Titanium Benchmarks for S10 Arch
#3105 opened
Jun 4, 2025 -
[Infra] Use Standard Strings in LibArchFPGA Physical Types
#3102 opened
Jun 3, 2025
8 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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Coding Style Guide
#3026 commented on
Jun 8, 2025 • 4 new comments -
parse_vtr_flow doesn't follow documentation
#2478 commented on
Jun 4, 2025 • 0 new comments -
System Verilog support is broken due to compilation error in F4PGA plugin
#2821 commented on
Jun 4, 2025 • 0 new comments -
Improve / suppress / control overly picky and frequent RR-graph warnings
#2199 commented on
Jun 6, 2025 • 0 new comments -
[WIP] Tileable Routing Resource Graph Builder
#2135 commented on
Jun 6, 2025 • 0 new comments -
[CI] Added System Verilog Regression Tests to GitHub Runners
#2885 commented on
Jun 5, 2025 • 0 new comments -
Congestion-Aware Initial Accumulated Cost
#3031 commented on
Jun 5, 2025 • 0 new comments -
Yosys upgrade WIP PR #2 for testing
#3093 commented on
Jun 6, 2025 • 0 new comments