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Issues: verilog-to-routing/vtr-verilog-to-routing
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[TestCoverage] Failing VTR Benchmarks on the 7Series Architecture
#3117
opened Jun 6, 2025 by
AlexandreSinger
Embed slang-yosys plugin as a SystemVerilog frontend for yosys
#3108
opened Jun 4, 2025 by
tarikgraba
[Infra] Use Standard Strings in LibArchFPGA Physical Types
#3102
opened Jun 3, 2025 by
AlexandreSinger
Use channel widths calculated from the rr-graph for drawing and linear congestion
#3100
opened Jun 2, 2025 by
soheilshahrouz
Remove duplicate ezgl from vtr, ensure documentation is built of the latest one
#3082
opened May 25, 2025 by
vaughnbetz
Clarify pack, place, route, analysis on vs. off reporting
#3039
opened May 14, 2025 by
vaughnb-cerebras
[STA] Post-Implementation STA Support for Dedicated Clock Network Modeling
#3027
opened May 7, 2025 by
AlexandreSinger
GUI not showing wires between connected CLBs despite highlighting
#3015
opened May 1, 2025 by
andrecavalcante
[Packer] Prepacker handling of pack pattern pins with net fanout > 1
#2996
opened Apr 22, 2025 by
amin1377
[Pack] Unneccesary mutation of the atom to clb lookup global context in packer
#2992
opened Apr 22, 2025 by
AmirhosseinPoolad
[Pack][Timing] Pre-Cluster Timing Analysis May Not Be Aware of Molecules
#2972
opened Apr 11, 2025 by
AlexandreSinger
Improve NoC arch tag documentation, and add ability to use equations in NoC tags
#2948
opened Mar 21, 2025 by
vaughnbetz
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