Several combinational assignments to register signals in arm_core.v

[WhiteNinjaZ]

I was running arm_core.v through vivado synthesis and noticed a few issues:

• o_stall is declared as an output but receives a sequential assignment on line 323
• read_miss is declared as a reg but recieves a combinational assignment on line 477
• push has the same issue on line 7202
• pop has the same issue on line 7203
• cache_stall being a register should technically not be assigned to the output port of a25_icache on line 842 and will cause an error in Vivado if synthesized.

Possible Solution

These signals should either be changed to a wire type to be consistent with their combinational assignments or the code should be changed to have these register signals assigned inside of an allways_ff block. In the case of o_stall, a separate register should be declared and feed into the output.

Steps to Reproduce

Run arm_core.v through vivado synthesis on the xc7a200tffv1156-1 part.