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opcodes: Reflect register name change for ARCv3 #74

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cc9820d
[arcv2/gdb] Make "arc*-" targets more restrict
Jan 11, 2022
bdc0226
[arcXX/gdb] Introduce "NONE" into "arc_isa" enum
Jan 26, 2022
a0fe340
[arc64/gdb] Add baremetal (with FPU) support
Apr 6, 2023
db13576
[arc64/gdb] Add newlib tdep
Oct 8, 2021
34dac72
[arc64/gdb] Add linux programs debugging support
Sep 13, 2021
326d2d5
[arc64/gdb] Add linux gdbserver support
Aug 24, 2021
72572eb
[arc32/gdb] Add baremetal support
Jan 11, 2022
94fa63d
[arc32/gdb] Add linux programs debugging support
Mar 25, 2022
004e795
[arc32/gdb] Add linux gdbserver support
Mar 25, 2022
e70f09b
arc: Update arc's gas tests
May 19, 2022
eeac81b
arc: Update binutils arc predicate for tests.
May 19, 2022
0da3a80
arc64: Update ARC64 support.
May 19, 2022
766c5af
arc64: Add new GAS tests for ARC64.
May 19, 2022
89732bd
arc64: Add new LD tests for ARC64.
May 19, 2022
fab8c2b
arc: Add Synopsys ARC64 machine to BFD.
May 19, 2022
f41cd5d
arc64: Add Synopsys new ARC64 machine.
May 19, 2022
14d7ac4
arc64: Update include files for ARC64.
May 19, 2022
04ec76b
arc: Add ARC64 support to GAS.
May 19, 2022
e4e0af5
arc64: New ARC64 instruction table
May 19, 2022
7ea7aa8
arc: Add Synopsys ARC64 instructions.
May 19, 2022
f0f7528
arc64: Reencode VPACK, VMIN, VMAX insns
claziss Jun 2, 2022
191a840
Fixes in arc64-tbl.h.
Jun 7, 2022
b84c993
Refactor tables for flags and operands.
Mar 25, 2022
5644ea7
Converted enums used for decoder floating points to macros.
Mar 25, 2022
a96572d
Added names to flags and operands.
Mar 25, 2022
4d1b331
arc64:Update stl/stdl masks and tests
claziss Jun 14, 2022
3dd3a6b
arc64: Update sth.di w6 instructions
claziss Jun 21, 2022
3808ec4
opcodes: fix negative relocations parameters
Jun 22, 2022
6f395b3
arcXX:Fix to TLS issue in new glibc.
Sep 21, 2022
4d46051
arc64: Revert stdl mask
claziss Oct 17, 2022
67e93a5
arc64: Fix sub_s.ne encoding
claziss Oct 18, 2022
871fafb
[arc64/opcodes] Add mmu_{rtp,ctrl,ttbc} auxiliary regs
Nov 7, 2022
754a108
[opcodes] arc: Fix the address for "isa_config" aux reg
Nov 21, 2022
c5211ab
[arc64/opcodes] Fix branch instructions class
Nov 29, 2022
e419bf9
ARC64: Add enter_s/leave_s instructions
claziss Dec 9, 2022
8b9e682
arc32: Add scond/llockd instructions
claziss Jan 13, 2023
cbd5144
arc32: Add all F16_SP_OPS
claziss Feb 10, 2023
ed5e6b8
arc64: Update STL and STDL instructions
claziss Jun 7, 2022
827754a
ALL: Compute sym value/section offset safe
claziss Mar 28, 2023
a112e2c
CLEANUP: Code cleanup
claziss Mar 30, 2023
2d9729a
CLEANUP: Code cleanup
claziss Mar 30, 2023
beabdc5
arc: Update neg<.f> 0,b encoding
claziss May 8, 2023
dcb2918
arc: Do not relocate TLS/GOT symbols which are resolved to zero
claziss May 4, 2023
e4e6413
arc: Remove the BFD_ASSERT and make safe next if-stmt
claziss May 9, 2023
9946044
arc64: Update VMAX/VMIN opcode for match ARC32 encoding
claziss Jun 14, 2023
51ad40a
arc64: Update bl_s with limm
claziss Jun 15, 2023
9053578
Relocations: Fix some 32 bit relocations
BrunoASMauricio Jun 19, 2023
b40e642
Relocations: Remove unused relocation ARC_32_ME_S
BrunoASMauricio Jun 19, 2023
4e744bb
arc64: Remove evaluae_expression
claziss Jul 4, 2023
1e5b811
arc: Update default target CPU to match GCC defaults
claziss Jul 4, 2023
72b0ca9
opcodes/arc: validate the {pop,push}dl_s operand
artemiy-volkov Jul 24, 2023
22b1bf4
arc: Fix alignment of the TLS Translation Control Block
claziss Aug 1, 2023
931df26
opcodes: Reflect register name change for ARCv3
luismgsilva Sep 5, 2023
1eacc22
opcodes: Update of Sign-Extended LIMM Name
luismgsilva Sep 6, 2023
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Converted enums used for decoder floating points to macros.
This convertion allows to pre-processor to further reduce
the entries in the opcode table.
  • Loading branch information
Cupertino Miranda authored and claziss committed Jul 4, 2023
commit 5644ea7fbe2b6f1c73cd9765ddb7a3d6779b52af
200 changes: 92 additions & 108 deletions include/opcode/arc.h
Original file line number Diff line number Diff line change
Expand Up @@ -691,114 +691,98 @@ typedef enum
#define ARC_NUM_ADDRTYPES 16

/*ARC64 floating point enums. */
enum FP_SIZE {
P_HALF = 0,
P_SINGLE = 1,
P_DOUBLE = 2
};

enum TPOF {
TOPF_FMADD = 0,
TOPF_FMSUB = 1,
TOPF_FNMADD = 2,
TOPF_FNMSUB = 3,
TOPF_VFMADD = 4,
TOPF_VFMSUB = 5,
TOPF_VFNMADD = 6,
TOPF_VFNMSUB = 7,

TOPF_VFMADDS = 0xC,
TOPF_VFMSUBS = 0xD,
TOPF_VFNMADDS = 0xE,
TOPF_VFNMSUBS = 0xF
};

enum DPOF {
DOPF_FADD = 0,
DOPF_FSUB = 1,
DOPF_FMUL = 2,
DOPF_FDIV = 3,
DOPF_FCMP = 4,
DOPF_FCMPF = 5,
DOPF_FMIN = 6,
DOPF_FMAX = 7,
DOPF_FSGNJ = 8,
DOPF_FSGNJN = 10,
DOPF_FSGNJX = 11,

DOPF_VFADD = 0x10,
DOPF_VFSUB = 0x11,
DOPF_VFMUL = 0x12,
DOPF_VFDIV = 0x13,
DOPF_VFADDS = 0x14,
DOPF_VFSUBS = 0x15,
DOPF_VFMULS = 0x16,
DOPF_VFDIVS = 0x17,

DOPF_VFUNPKL = 0x18,
DOPF_VFUNPKM = 0x19,
DOPF_VFPACKL = 0x1a,
DOPF_VFPACKM = 0x1b,
DOPF_VFBFLYL = 0x1c,
DOPF_VFBFLYM = 0x1d,
DOPF_VFADDSUB = 0x1e,
DOPF_VFSUBADD = 0x1f

};

enum SOPF {
SOPF_FSQRT = 0,
SOPF_VFSQRT = 1,
SOPF_VFEXCH = 2
};

enum COPF {
COPF_FMOV = 0,
COPF_VFMOV = 1,
};

enum CONVOPS {
FUINT2S = 0,
FS2UINT = 0,
FINT2S = 0,
FS2INT = 0,
FSRND = 0,
F2UINT_RZ = 0,
FSINT_RZ = 0,
FSRND_RZ = 0,
FMVI2S = 0,
FMVS2I = 0,
FS2H = 0,
FH2S = 0,
FS2H_RZ = 0,

FUINT2D = 1,
FS2UL = 1,
FINT2D = 1,
FS2L = 1,
FS2D = 1,
FS2UL_RZ = 1,
FS2L_RZ = 1,

FUL2S = 2,
FD2UINT = 2,
FL2S = 2,
FD2INT = 2,
FD2S = 2,
FD2UINT_RZ = 2,
FD2INT_RZ = 2,

FUL2D = 3,
FD2UL = 3,
FL2D = 3,
FD2L = 3,
FDRND = 3,
FD2UL_RZ = 3,
FD2L_RZ = 3,
FDRND_RZ = 3,
FMVL2D = 3,
FMVD2L = 3,
};
#define P_HALF 0
#define P_SINGLE 1
#define P_DOUBLE 2

#define TOPF_FMADD 0
#define TOPF_FMSUB 1
#define TOPF_FNMADD 2
#define TOPF_FNMSUB 3
#define TOPF_VFMADD 4
#define TOPF_VFMSUB 5
#define TOPF_VFNMADD 6
#define TOPF_VFNMSUB 7
#define TOPF_VFMADDS 0xC
#define TOPF_VFMSUBS 0xD
#define TOPF_VFNMADDS 0xE
#define TOPF_VFNMSUBS 0xF

#define DOPF_FADD 0
#define DOPF_FSUB 1
#define DOPF_FMUL 2
#define DOPF_FDIV 3
#define DOPF_FCMP 4
#define DOPF_FCMPF 5
#define DOPF_FMIN 6
#define DOPF_FMAX 7
#define DOPF_FSGNJ 8
#define DOPF_FSGNJN 10
#define DOPF_FSGNJX 11
#define DOPF_VFADD 0x10
#define DOPF_VFSUB 0x11
#define DOPF_VFMUL 0x12
#define DOPF_VFDIV 0x13
#define DOPF_VFADDS 0x14
#define DOPF_VFSUBS 0x15
#define DOPF_VFMULS 0x16
#define DOPF_VFDIVS 0x17
#define DOPF_VFUNPKL 0x18
#define DOPF_VFUNPKM 0x19
#define DOPF_VFPACKL 0x1a
#define DOPF_VFPACKM 0x1b
#define DOPF_VFBFLYL 0x1c
#define DOPF_VFBFLYM 0x1d
#define DOPF_VFADDSUB 0x1e
#define DOPF_VFSUBADD 0x1f

#define SOPF_FSQRT 0
#define SOPF_VFSQRT 1
#define SOPF_VFEXCH 2

#define COPF_FMOV 0
#define COPF_VFMOV 1

#define FUINT2S 0
#define FS2UINT 0
#define FINT2S 0
#define FS2INT 0
#define FSRND 0
#define F2UINT_RZ 0
#define FSINT_RZ 0
#define FSRND_RZ 0
#define FMVI2S 0
#define FMVS2I 0
#define FS2H 0
#define FH2S 0
#define FS2H_RZ 0

#define FUINT2D 1
#define FS2UL 1
#define FINT2D 1
#define FS2L 1
#define FS2D 1
#define FS2UL_RZ 1
#define FS2L_RZ 1

#define FUL2S 2
#define FD2UINT 2
#define FL2S 2
#define FD2INT 2
#define FD2S 2
#define FD2UINT_RZ 2
#define FD2INT_RZ 2

#define FUL2D 3
#define FD2UL 3
#define FL2D 3
#define FD2L 3
#define FDRND 3
#define FD2UL_RZ 3
#define FD2L_RZ 3
#define FDRND_RZ 3
#define FMVL2D 3
#define FMVD2L 3

#ifdef __cplusplus
}
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