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opcodes: Reflect register name change for ARCv3 #74

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cc9820d
[arcv2/gdb] Make "arc*-" targets more restrict
Jan 11, 2022
bdc0226
[arcXX/gdb] Introduce "NONE" into "arc_isa" enum
Jan 26, 2022
a0fe340
[arc64/gdb] Add baremetal (with FPU) support
Apr 6, 2023
db13576
[arc64/gdb] Add newlib tdep
Oct 8, 2021
34dac72
[arc64/gdb] Add linux programs debugging support
Sep 13, 2021
326d2d5
[arc64/gdb] Add linux gdbserver support
Aug 24, 2021
72572eb
[arc32/gdb] Add baremetal support
Jan 11, 2022
94fa63d
[arc32/gdb] Add linux programs debugging support
Mar 25, 2022
004e795
[arc32/gdb] Add linux gdbserver support
Mar 25, 2022
e70f09b
arc: Update arc's gas tests
May 19, 2022
eeac81b
arc: Update binutils arc predicate for tests.
May 19, 2022
0da3a80
arc64: Update ARC64 support.
May 19, 2022
766c5af
arc64: Add new GAS tests for ARC64.
May 19, 2022
89732bd
arc64: Add new LD tests for ARC64.
May 19, 2022
fab8c2b
arc: Add Synopsys ARC64 machine to BFD.
May 19, 2022
f41cd5d
arc64: Add Synopsys new ARC64 machine.
May 19, 2022
14d7ac4
arc64: Update include files for ARC64.
May 19, 2022
04ec76b
arc: Add ARC64 support to GAS.
May 19, 2022
e4e0af5
arc64: New ARC64 instruction table
May 19, 2022
7ea7aa8
arc: Add Synopsys ARC64 instructions.
May 19, 2022
f0f7528
arc64: Reencode VPACK, VMIN, VMAX insns
claziss Jun 2, 2022
191a840
Fixes in arc64-tbl.h.
Jun 7, 2022
b84c993
Refactor tables for flags and operands.
Mar 25, 2022
5644ea7
Converted enums used for decoder floating points to macros.
Mar 25, 2022
a96572d
Added names to flags and operands.
Mar 25, 2022
4d1b331
arc64:Update stl/stdl masks and tests
claziss Jun 14, 2022
3dd3a6b
arc64: Update sth.di w6 instructions
claziss Jun 21, 2022
3808ec4
opcodes: fix negative relocations parameters
Jun 22, 2022
6f395b3
arcXX:Fix to TLS issue in new glibc.
Sep 21, 2022
4d46051
arc64: Revert stdl mask
claziss Oct 17, 2022
67e93a5
arc64: Fix sub_s.ne encoding
claziss Oct 18, 2022
871fafb
[arc64/opcodes] Add mmu_{rtp,ctrl,ttbc} auxiliary regs
Nov 7, 2022
754a108
[opcodes] arc: Fix the address for "isa_config" aux reg
Nov 21, 2022
c5211ab
[arc64/opcodes] Fix branch instructions class
Nov 29, 2022
e419bf9
ARC64: Add enter_s/leave_s instructions
claziss Dec 9, 2022
8b9e682
arc32: Add scond/llockd instructions
claziss Jan 13, 2023
cbd5144
arc32: Add all F16_SP_OPS
claziss Feb 10, 2023
ed5e6b8
arc64: Update STL and STDL instructions
claziss Jun 7, 2022
827754a
ALL: Compute sym value/section offset safe
claziss Mar 28, 2023
a112e2c
CLEANUP: Code cleanup
claziss Mar 30, 2023
2d9729a
CLEANUP: Code cleanup
claziss Mar 30, 2023
beabdc5
arc: Update neg<.f> 0,b encoding
claziss May 8, 2023
dcb2918
arc: Do not relocate TLS/GOT symbols which are resolved to zero
claziss May 4, 2023
e4e6413
arc: Remove the BFD_ASSERT and make safe next if-stmt
claziss May 9, 2023
9946044
arc64: Update VMAX/VMIN opcode for match ARC32 encoding
claziss Jun 14, 2023
51ad40a
arc64: Update bl_s with limm
claziss Jun 15, 2023
9053578
Relocations: Fix some 32 bit relocations
BrunoASMauricio Jun 19, 2023
b40e642
Relocations: Remove unused relocation ARC_32_ME_S
BrunoASMauricio Jun 19, 2023
4e744bb
arc64: Remove evaluae_expression
claziss Jul 4, 2023
1e5b811
arc: Update default target CPU to match GCC defaults
claziss Jul 4, 2023
72b0ca9
opcodes/arc: validate the {pop,push}dl_s operand
artemiy-volkov Jul 24, 2023
22b1bf4
arc: Fix alignment of the TLS Translation Control Block
claziss Aug 1, 2023
931df26
opcodes: Reflect register name change for ARCv3
luismgsilva Sep 5, 2023
1eacc22
opcodes: Update of Sign-Extended LIMM Name
luismgsilva Sep 6, 2023
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23 changes: 22 additions & 1 deletion bfd/Makefile.am
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,7 @@ ALL_MACHINES = \
cpu-alpha.lo \
cpu-amdgcn.lo \
cpu-arc.lo \
cpu-arc64.lo \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
Expand Down Expand Up @@ -182,6 +183,7 @@ ALL_MACHINES_CFILES = \
cpu-alpha.c \
cpu-amdgcn.c \
cpu-arc.c \
cpu-arc64.c \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
Expand Down Expand Up @@ -263,6 +265,7 @@ ALL_MACHINES_CFILES = \
# The .o files needed by all of the 32 bit vectors that are configured into
# target_vector in targets.c if configured with --enable-targets=all.
BFD32_BACKENDS = \
arc-plt.lo \
aout-cris.lo \
aout-ns32k.lo \
aout32.lo \
Expand Down Expand Up @@ -398,6 +401,7 @@ BFD32_BACKENDS = \
xtensa-modules.lo

BFD32_BACKENDS_CFILES = \
arc-plt.c \
aout-cris.c \
aout-ns32k.c \
aout32.c \
Expand Down Expand Up @@ -430,7 +434,6 @@ BFD32_BACKENDS_CFILES = \
elf-vxworks.c \
elf.c \
elf32-am33lin.c \
elf32-arc.c \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
Expand Down Expand Up @@ -540,6 +543,8 @@ BFD64_BACKENDS = \
elf32-aarch64.lo \
elf64-aarch64.lo \
elfxx-aarch64.lo \
elf32-arc64.lo \
elf64-arc64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
Expand Down Expand Up @@ -681,6 +686,7 @@ SOURCE_CFILES = \

BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
elf32-arc.c elf64-arc64.c elf32-arc64.c\
elf32-ia64.c elf64-ia64.c \
elf32-loongarch.c elf64-loongarch.c \
elf32-riscv.c elf64-riscv.c \
Expand Down Expand Up @@ -842,6 +848,21 @@ elf64-aarch64.c : elfnn-aarch64.c
$(AM_V_at)echo "#line 1 \"elfnn-aarch64.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@

elf32-arc.c : elfnn-arc.c
rm -f elf32-arc.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA//g < $< >> $@

elf64-arc64.c : elfnn-arc.c
rm -f elf64-arc64.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/64/g -e s/AA/64/g < $< >> $@

elf32-arc64.c : elfnn-arc.c
rm -f elf32-arc64.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA/64/g < $< >> $@

elf32-ia64.c : elfnn-ia64.c
$(AM_V_at)echo "#line 1 \"elfnn-ia64.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@
Expand Down
27 changes: 26 additions & 1 deletion bfd/Makefile.in
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -554,6 +554,7 @@ ALL_MACHINES = \
cpu-alpha.lo \
cpu-amdgcn.lo \
cpu-arc.lo \
cpu-arc64.lo \
cpu-arm.lo \
cpu-avr.lo \
cpu-bfin.lo \
Expand Down Expand Up @@ -637,6 +638,7 @@ ALL_MACHINES_CFILES = \
cpu-alpha.c \
cpu-amdgcn.c \
cpu-arc.c \
cpu-arc64.c \
cpu-arm.c \
cpu-avr.c \
cpu-bfin.c \
Expand Down Expand Up @@ -719,6 +721,7 @@ ALL_MACHINES_CFILES = \
# The .o files needed by all of the 32 bit vectors that are configured into
# target_vector in targets.c if configured with --enable-targets=all.
BFD32_BACKENDS = \
arc-plt.lo \
aout-cris.lo \
aout-ns32k.lo \
aout32.lo \
Expand Down Expand Up @@ -854,6 +857,7 @@ BFD32_BACKENDS = \
xtensa-modules.lo

BFD32_BACKENDS_CFILES = \
arc-plt.c \
aout-cris.c \
aout-ns32k.c \
aout32.c \
Expand Down Expand Up @@ -886,7 +890,6 @@ BFD32_BACKENDS_CFILES = \
elf-vxworks.c \
elf.c \
elf32-am33lin.c \
elf32-arc.c \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
Expand Down Expand Up @@ -997,6 +1000,8 @@ BFD64_BACKENDS = \
elf32-aarch64.lo \
elf64-aarch64.lo \
elfxx-aarch64.lo \
elf32-arc64.lo \
elf64-arc64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
Expand Down Expand Up @@ -1137,6 +1142,7 @@ SOURCE_CFILES = \

BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
elf32-arc.c elf64-arc64.c elf32-arc64.c\
elf32-ia64.c elf64-ia64.c \
elf32-loongarch.c elf64-loongarch.c \
elf32-riscv.c elf64-riscv.c \
Expand Down Expand Up @@ -1428,6 +1434,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-ns32k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-plt.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archive.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archive64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archures.Plo@am__quote@
Expand Down Expand Up @@ -1461,6 +1468,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-amdgcn.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-avr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bfin.Plo@am__quote@
Expand Down Expand Up @@ -1556,6 +1564,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-am33lin.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arc64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-avr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-bfin.Plo@am__quote@
Expand Down Expand Up @@ -1624,6 +1633,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-amdgcn.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-arc64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
Expand Down Expand Up @@ -2340,6 +2350,21 @@ elf64-aarch64.c : elfnn-aarch64.c
$(AM_V_at)echo "#line 1 \"elfnn-aarch64.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@

elf32-arc.c : elfnn-arc.c
rm -f elf32-arc.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA//g < $< >> $@

elf64-arc64.c : elfnn-arc.c
rm -f elf64-arc64.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/64/g -e s/AA/64/g < $< >> $@

elf32-arc64.c : elfnn-arc.c
rm -f elf32-arc64.c
$(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA/64/g < $< >> $@

elf32-ia64.c : elfnn-ia64.c
$(AM_V_at)echo "#line 1 \"elfnn-ia64.c\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@
Expand Down
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