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mcs51: fix destination RAM type in XCHD A, @R0/@R1 #14289

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Merged
merged 1 commit into from
Oct 8, 2025
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mcs51: fix destination RAM type in XCHD A, @R0/@R1 #14289

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2 changes: 1 addition & 1 deletion src/devices/cpu/mcs51/mcs51ops.hxx
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Original file line number Diff line number Diff line change
Expand Up @@ -930,7 +930,7 @@ OPHANDLER( xchd_a_ir )
ir_data = IRAM_IR(R_REG(r)); //Grab data pointed to by R0 or R1
acc = ACC; //Grab ACC value
SET_ACC((acc & 0xf0) | (ir_data & 0x0f)); //Set ACC to lower nibble of data pointed to by R0 or R1
IRAM_W(R_REG(r), (ir_data & 0xf0) | (acc & 0x0f)); //Set data pointed to by R0 or R1 to lower nibble of ACC
IRAM_IW(R_REG(r), (ir_data & 0xf0) | (acc & 0x0f)); //Set data pointed to by R0 or R1 to lower nibble of ACC
}

//XRL data addr, A /* 1: 0110 0010 */
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