Difference between Microprocessor and Microcontroller Weta Rees + Itcontains only CPU % CPU, Memory, 10, Timer are on single chip. + Designer decides size of ROM, RAM & 10 handling. ‘ Fixed size of ROM, RAM & 10 handling. ‘4 Architecture : Von numen [Mostly]. % Architecture : Harvard [Mostly]. + Itis better in Multi-Tasking, Relatively weak in Multi-Tasking. ‘+ General Purpose. {Like our Main Computer) ‘Application Specific Purpose. (Embedded System) +b High speed and High Cost. ‘% Relatively Low speed and low cost. It requires more hardware to be interfaced, Itrequires less hardware to be interfaced ‘+ High Power Consumption % Low Power Consumption ¥ + Does not support bit addressability [Mostly]. © Support bit addressability [Mostly]. ++ Examples : 8085, 8086, Core i3. Core IS. Corei7. AMD Processor. ¢ Examples : 8051. AVR. PIC. ARMFeatures of 8051 uC ** Features of 8051 Microcontroller 18051 is complete computer system built on one Chip. It has CPU, RAM, ROM, Serial port, Parallel Port, Interrupt, Timer on single chip. . 8051 operates at 12MHz clock frequency. 8051 has 8 bits of ALU. 8051 has 8 bits of Data lines. Q 8051 follows Harvard architecture. {So, it has separate memory for program and data storage.) Harvard Architecture has Separate memory for program and data. Program is stored in ROM and Data in RAM.Features of 8051 uC “Features of 8051 Microcontroller 2.8051 is complete computer system built on one Chip. It has CPU, RAM, ROM, Serial port, Parallel Port, Interrupt, Timer on single chip. C8051 operates at 12MHz clock frequency. 8051 has 8 bits of ALU. ° 8051 has 8 bits of Data lines. Q 2051 follows Harvard architecture. {So, it has separate memory for program and data storage.} 8051 has 4K8 of internal ROM for program storage. C8051 has 128 bytes of RAM for data storage. C8051 has Four 8 bits of 10 ports. {This ports can be used for interfacing of peripherals like Keyboard, display, stepper motor, LEDs & switches etc} 8051 has a serial port synchronous and asynchronous communication. C2051 has two 16 bits ‘UP’ timers. {which can be used for delay generation.) Q 8051 has Five interrupts operating at priority levels. 8051 has two power saving modes. {Idle mode and Power down mode} (8051 has 16 bits of address bus which can be used to interface external memory of RAM or ROM. {64KB can be interfaced with 16 address lines.} Q.8051 is efficient in embedded system which saves cost, power and makes circuit compact.PIN Diagram of 8051 uC * Power Supply C8052 has Vec = +5V and Vss = Reference (Ground) ¢ XTALL and XTAL2 Crystal is connected in between these two pins. G12 MHz of crystal clock is provided. Qin serial communication, operating frequency is chosen to be 11.0592MHz, in order to get standard universal baud rates. o> RESET 80: itis used to RESET 8051 Microcontroller. es Q On reset PC becomes OOOOH, This address is called PIN Dia RESET vector address. C From this address, 8051 executes BIOS programs. BIOS program is used to set up the system and make system ready for end user. +h ALE~ Address Latch Enable ‘2 itis used to separate Address and Data. Q In 8051, ADO-AD7 lines are time multiplexed. IFALE = 1, bus carries Address. FL ALE =a hue carrine MiataPIN Diagram of 8051 uC ++ EA- Enable External Access Q 8051 has internal 4KB ROM. Of EA = 0, 8051 will discards internal 4KB ROM and external ROM memory location will starts from 00H. Q If EA = 1, 8051 will consider internal 4KB ROM with starting address OOOOH to ending address OFFFH and External ROM memory location will starts from. 1000H. * PSEN - Program Status Enable C1 8051 has 16 bits Address AO-A1S. by that we can interface 64KB of external ROM and 64K of external RAM, making it total 128KB memory space. Both have same address rangg OOOOH to FFFFH. Q PSEN reads data from external ROM. GRD and WR are used for read and write of external RAM, Q PSEN is referred as program status enable, as it allows program to be read from external ROM.PIN Diagram of 8051 uC + Port 2 ~ {P2.0-P2.7}/A15-A8 Q On port 2, 8051 has 8 pins P2.0-P2.7 Q We can perform 8 bits operation on entire port. porno h0.0-P0-7) CQ) We can also perform 1 bit operation on port 2. {Like we can sot bit, clear bit and complement bit) Port 2 also carries Address lines A15 ~ AB. + Port 3 - {P3.0-P3.7) D On port 3, 8051 has 8 pins P3.0-P3.7 O We can perform 8 bits operation on entire port. O We can also perform 1 bit operation on port 3. {Like ‘we can set bit, clear bit and complement bit} Port 3 also have many alternate Functions RxD} Serial st RxD {P3.0) & TxD {P3.1) Tx | Comm. "RxD and RxD pins are used for serial communication, INTO} INTO (3.2) & INT (P3.3) INT Uinterrupts They are Hardware Interrupt of 8051, in which INTO 70 | sever has higher priority. TO {P3.4) & T1{P3.5) WR] Control _Q1 They are Timer clock input of 8051 Port 1{P1.0-P1.7) Port 2 {2.0-P2.7) AIS-AB, Port 3 {P3.0-P3.7} Rp J Signals < WR {P3.6) & RD{P3.7} Control Signals O They are used for read and write operation for RAM.10 Ports of 8051 uC oy Povt 0 LP 0.0 40 0,4) Posl-2 £P2.0 46 PL.ZY fs o> Poti {prote rsa) WEF % fost-3 4 P3040 Paz} -Te% R ft Soil Comm.” ¥ - INTO % INTT Qvhownety ~ To & Ty {Timer} - Fo 2 Ge QRAM Gonteo!10 Ports of 8051 uC Vee PORT OBIT10 Ports of 8051 uC Read ‘Add/Data € ternal < lh | ee Read PORT 0 BIT Pin10 Ports of 8051 uC Add/Data [Control PORT OBIT Read Address Vee Latch Internal] Bus Write Latch Control Mux pe PORT 2 BIT Pin Read Latch Internal] Bus Write Latch Read Output Internal Bus | Write. Latch Functions PORT 1 BIT moat Functions PORT 3 BITBlock Diagram of 8051 uC External errs Ald, Reena is OOOOH +o OFFFH.Block Diagram of 8051 uC External Interrupts Timer } Clock Input Po p2, PA\P3 THD RxD 12M —— Ap,-aose"/8 Ag FicALU, A, B, PC, DPTR, SP & PSW of 8051 External Interrupts 77 + ALU Arithmetic & Logie Unit iit performs 8 bits of arithmetic & Logic operations. Q It can also perform one bit operations. ACARRL ;Compliment PO.3 pin + Accumulator A O Accumulator is 8 bits register. Q Most of Arithmetic and Logical operations are performed with respect to accumulator. Example: ‘ADD A,RO JAMAARO ANLA.RL JACAAND RI + Register B O itis 8 bits register. O Itis dedicated for Multiplication and Division. O Exampl P2, PL PB os MULAB jBACAXB Address / Data Divas © :A/B, stores quotient in A& remainder in BALU, A, B, PC, DPTR, SP & PSW of 8051 + SP— Stack Pointer O itis 8 bits register. O Itholds address of top of stack. O The stack is present in internal RAM. O Internal RAM Address is from OOH to 7FH. O itis used for PUSH and POP Instructions. 0 On RESET, SP of 8051 indicates 07H address of internal RAM. PSW - Program Status Word CPitis 8 bits register. O itis also called the “Flag Register”. O It gives status after every instruction execution In program. O The flags can also be changed by programme! O PSWis bit addressable regist O Example: SETB PSW.2 sPSW.2=1 CLR PSW.2 sPSW.2=0 External InterruptsALU, A, B, PC, DPTR, SP & PSW of 8051 + PC- Program Counter O itis 16 bits register. O It holds address of next instruction in program memory of ROM, } 1 PC gets incremented automatically as soon as any instruction is fetched. ba Incase of branch, new address is loaded in PC. Input DPTR- Data Pointer O itis 16 bits register. O Itholds address of Data in memory of RAM. O PTR is further divided into two registers of bits {OPH — Higher Byte & DPL— Lower Byte}. O itis used by programmer to transfer data from external RAM. O It can also be used as pointer for look up table in ROM, using indexed Addressing Mode. O Exampl Po P2, PL P3. MOVXA,@DPTR A will get data from RUF RAM pointed by DPTR Address / Data MOVCA,@A+DPTR;A will get data from e ROM pointed by DPTR+A.PSW / Flag Register in 8051 uC + P= Parity Flag Q P=1, Odd Parity {Odd Number of 2's in result} Ol P=0, Even Parity {Even Number of 1's in result) + OVR- Overflow Flag Q ovr =1, signed overflow OQ OvR=0, No Signed overflow © Ithappens when result goes beyond 127 to -128. O Alter overflow, sign of result {SB} becomes wrong. + RS~ Register Bank Select D RS =00, Register Bank 0, {Default} © RS=01, Register Bank 1 RS= 10, Register Bank 2 O RS= 11, Register Bank 3 Q By CLR and SETB instructions we can select register bank. O Example cuR PSW.a SETB PSW.3 ;Here RS = 01 means bank 1 is selected PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 m1 A=CCH 1100 1100 R1=EGH 1110 0110 A=B2H 1011 0010 Example: ADD ARI 4 FO~ User Defined Fi O Set by user using SETB PSW.S OF Clear by user using CLR PSW.S + AC- Axillary Corry Flog 0 AC=1, Nibble to Nibble Carry 1D AC=0, No Nibble to Nibble Carry + CY Carry Flag O cy=1, Result has Carry. 1D cv=0, Result has no Carry.ROM Organization in 8051 uC “+ 8051 Microcontroller Memory Q 8052 can have four different memories: * Internal ROM {4KB} * Internal RAM (128 byte} ‘External ROM {Max 64KB) External RAM {Max 64KB} Architecture of 8051 Microcontroller Q 8051 follows Harvard Architecture. So, with 8051 Program memory is ROM and Data memory is RAM. < Applications of 8051 Microcontroller Q Microcontroller is used in many embedded system applications. {Remote control, Microwave Oven, Watching Machine etc.) Q Once controller is embedded in application, program of controller should be fixed and it should be stored in ROM. G1 Data may change in application like time, ‘temperature and it will be stored in RAM. O Fixed data will be stored in ROM as look up table. {ASCII, SSD etc.} Only Internal ROM FA=1 reer ROM Organization Internal & External Only External ROM. ROM EA=1 FA=0 Internal ROM 4KB. eer Cr CTL hyl Er)Internal RAM Structure in 8051 C + 8051 Microcontroller Register Bank in RAM © 8051 has four register banks. Each register bank has Elght registers RO-R7. 39 gvaqg op (—7FH O Selection of register bank can be done by two bits of PSW register, by | “Rata gae PSW.3 and PSW.4 we can select any register bank. Seana CLR PSW.8 general pea SETS PSW.3 ;Here RS = 01 means bank 1 is selected |. Cl RAM address 00H to 1FH holds four register banks. dH , MoV A,Ro ;Copy RO into A 16 Bytes of fp MOV A,08H __;Copy RO of register bank 1 into A RAM for Bit, Bist, 4 8051 Microcontroller Bit Addressable Area in RAM wise Area CERRO 16 Byte of RAM from 20H to 2FH holds bit addressable area in internal | Addressing OE 0D .... 09¢ RAM of 8051 microcontroller. 20H O 16x 8= 128 Addressable bits in these area. aFH Oi These bits are addressed as per OOH to 7FH, in total 128 bits. ion O These locations can have bit as well byte wise operations. 32 Bytes DH SETB7FH ;Set MSB of 2FH RAM location of RAM CUR o8H ;Clear LSB of 214 RAM location is 104 MOV 20H, #FFH Set all bits 20H RAM locations Register Orn “+ 8051 Microcontroller General Purpose Area in RAM {Scratchpad RAM) bank 08H G80 Byte of RAM from 30H to 7FH holds general purpose area in internal RAM of 8051 microcontroller. It can be used for general purpose operations.Stack of 8051 uC O Stack of 8052 operating with respect to only memory of | Internal RAM of 8051 microcontroller. Aad | Cota Q Stack memory works as per LIFO {Last In First Out). boat O Stack is used to store return address during ISRs and | Cosi[——] Subroutines. : sp—fo7H Tox] G Stack is also used by programmer using PUSH and POP Instructions. Before MOV SP,#2FH O Top of stack is pointed by SP register. sPis8 bits regist i Add | Data On RESET of 8051, SP holds 07H address. i [sin Q Programmer can change the SP address as per their | SP —+[ 30H [11H | requirement. Range is available from OOH to 7FH as | a internal RAM size is of 128 bytes. | MOV SP,H20H ——_;SP holds 20H address of RAM i Biter AusH Ra 1 Program to access stack memory using PUSH and POP! MoV R1,#1H i = Mov R2,#22H [moa MOV SP,#2FH i sp—[3on Tati PUSH RI i | 2FH | xx | PUSH R2 POP R3 After POP R3 ; R3 = 22H POP R4 Add | Data [3aH [30H sp —+[2FH | After MOV SP,#2FH Add | Data sp —[3in | 22n_| [30H Tain | [2rH [xx] After PUSH R2 Add | Data [31H [22H | [30H Tah | se— [Gen Dox] After POP R4 ;R4=11HSFRs of 8051 uC Ql SFR~ Special Function Registers with size of 8 bits. Functo i SFRs are On chip registers for special functions of 8051. {Timers, Counter, 10, Serial Communication, | Pata and Interrupt, Power Saving Modes, etc.} “es There are 21 SR registers with 8051, which are sy used with thelr addresses In instructions to reduce | [Wi"e' 0 Address taterat Memory HWA number of opcodes in 8051. i Ades tera Memony We have seen that internal RAM is used with © fotateh port sa =o addressing from OOH to 7FH. Likewise SFRs are used | with addressing in between 80H to FFH. This addressing supports byte and bit wise operations. C This addressing reduces numbers of opcodes for total instructions. =a © otmtennot TBH SON SeristPortControt = BMF = 9B | Seralpor outa tatier 9a MA ea a ‘SETB PO.0 ;SETB has opcode & P0.0 has tmer/Countar bs mH NA . address 80H a re a eo C8052 supports bit wise special functions and byte Timer Lowery wise special functions, if addressing is not done with SFRs then there would be to many opcodes and that will make too much complicated instruction decode circuit.Editor, Compiler, Assembler, Linker & Loader oo oo a In Editor we write programs for Microcontroller. Programs may be written in Assembly Language or Higher Level Source Object Complier Fie. Assembler Language {C Languay By writing program we generate source file. Assembler machine code or object file. It also shows errors if any syntax!) Once It is used to convert Assembly language into error is there in program. Complier it is used to convert Higher Level language into machine code or object file. It also shows errors if any syntax error is there in program. It also gives warnings if it is there with programs. Linker : It is linking all the object files of compiler and assembler with the use of library. Q twill generate executable files. © Loader: It is used to load executable files into the memory of microcontroller. program is loaded microcontroller can execute requirement of USER. into it as memory, per theData Types & Assembler Directives of 8051 C Data Types of 8051 microcontroller ‘8051 Microcontroller supports Binary, Decimal and Hexadecimal | data formats. i Example: + MOV A,#00110110B ; A -- 00110110, Binary 00110110 is loaded | « in A which is equivalent of 36H. Mov A.#15 A 15, Decimal 15 is loaded in A which is | « ‘equivalent of OFH. MOV A,HISH A+ 15H, Hexadecimal 15H is loaded in A. Assembler Directives of 8051 microcontroller Assembler directives are also referred as pseudo Opcodes. ‘Assembler directives are not Instructions, so they are not! ‘executed by MPU, it is used to give directions to assembler. ORG {Origin} ‘ORG 10008 (ORG directives is used indicate beginning address. After writing ORG 1000H, program or data will be stored at 1000H memory location. ‘Some assembler may use .ORG, so you need check that as well. If you don't write H after number then it will consider decimal address with ORG. END {Terminate} Itis used to END source file (.asm file). Anything after END directive will be ignored by assembler. QU {Equate) It is used to define constant without occupying a memory location. Itis used for constant values in program. pp EQU2SH constant with pp label MOV}, pp constant loaded in R1 DB {Define Byte) Itis used to define byte data. Here, 8 bits (Byte) number can be decimal, Hexadecimal, Binary ‘0r ASCII number. ‘ORG 1000H B25 data 1 is defined by 25 decimal no. 8 25H ‘data 2 is defined by 25H Hex no. 8 001100118, fata 3 is defined by 33H binary no. pew sdata 4 is defined by ASCI of A. DB “Er” data S is defined by string of ASCII.os. Addressing Modes of 8051 uC ‘Addressing mode: The Various formats of specifying the operands are called addressing modes. Immediate Addressing Mode {tn this Addressing mode, data (1byte/2bytes) specified in instruction itself. O Data is specified by “#’ symbol before data in the instruction. os. Example: MOV A,H1SH jan 15H MOV DPTR,H1000H__; DPTR + 1000H Register Addressing Mode In this Addressing mode, data is specified by registers in Instruction. The permitted registers are A, R7, R6, ., RO. Example: MOV A.R2 ArRR MOV R2,A, REA ‘MOV R1,R2 Not Allowed with 8051, Y Direct Addressing Mode © in this Addressing mode, address of operand is given in instruction, © Only internal RAM and SFR address are allowed. ° Example: MOV A,35H_ sA+ [35H] ‘Mov A,80H A+ [80H], Content of port 0s [80H] MOV30H.35H 13H] ~ [35H] Indirect Addressing Mode In this Addressing mode, address of operand will be given by register. Internal and External RAM can be accessed by this mode. Internal RAM with Bbits of addressing, “@” is used here MOVA,@R1 pA (RA) MoV @R2,A 31R2]— A “External RAM with 16bits of addressing by OPTR, "x" is used here MOVX A,@DPTR iA-- [0PTR] MOVXx @DPTR,A [OPTR] A + External RAM with bits of addressing by RO or R1 MOVX A,@R1 3 A~[R1), If R1 is 25H then {3} = [o02sH) }1RO] ~ A, If is 35H then {RO} = (0035H) Indexed Addressing Mode This addressing mode is used to access data from code memory {Internal ROM or External ROM). In instruction, we use ‘C’ to operate with Indexed Addressing mode. Exampl MOVCA,@A+DPTR ; A [ASDPTR] MOVCA,@APC A+ [A+PC] | | | | i | iArithmetic Instructions of 8051 C Y Addition instructions ¥ Increment instructions Q ADD = It will Add Accumulator data with & bits & stores result (1 INC - It will increment Register, Pointer or data of memory into A. locations. ADD A, #50H 7A A+50H INCA ;AA4+1 ADDA,R1 pA AFI INCRI ;R1-R14+1 ADD A, 17H pA A+ [17H] INC 2SH_; [25H] - [25H] +1 ADD A, @R1 A+ [RI] INC @Ri ; [R1] — [RA] +1 OQ ADDC - It will Add Accumulator data with 8 bits along with INC DPTR; DPTR — DPTR +1 (Corry 6 stores result to A. v Decrement instructions ADDCA,#50H Ax A+S0H+ Carry C2 DEC ~ It will decrement Register, Pointer or data of memory ADDCA, R1 pA A+R1 +4 Carry locations. ADDCA, 17H + A+ [17H] + Carry DECA —A-1 ADDCA,@R1 = ; Ax A+[R1] + Carry DECRI ;R1~-R1-1 ¥ Subtraction instructions DEC 25H ; [25H] [25H] -1 2 suBe - it will Sub Accumulator data with 8 bits along with DEC @R1; [R1) — [R1}-2 Carry & stores result into A. DEC DPTR ; Does not exists SUBBA,#50H =; A A-SOH- Carry SUBB A, R1 + A-RI1- Carry SUBB A, 17H -A- [17H] - Carry SUBBA,@R1 =; A A-[R1] - CarryArithmetic Instructions of 8051 uC plication instruction MUL AB ~ It will Multiply A and 8 and Answer will be stored in BA where B hold higher Byte and A hold Lower Byte. MULAB ; (Burigher nyte Atower nyte) — AXB Y Division instruction IV AB - It will Divide A by B and Answer remainder will be stored in B & Quotient will be stored in A. DIVAB 5 (Bremainder Aguotient) — A/B Y Decimal Adjustment instruction DA A~It will be used after ADD instruction, {tis used to convert that given Hex addition in BCD addition. ‘Normal Addition is done by ADD that is Binary or Hex Addition. {After when you use DA A, it adjust that addition In BCD form. DA A performs following adjustments to show given addition in BCD addition. I Lower Nibble > 9 or Auxiliary Carry is 1 then Add OGH with A I Higher Nibble > 9 or Carry is 1 then Add 6OH with A oo ooooo Example: ADD A, RI pACAERL DAA ; BCD Addition Adjustment AC=L A=38H A=61H o6H ‘A= 67H a. A= 60H A=99H R1= 70H ‘A= DOH 60H GH A=30H —— Carry =1 ‘AL= 98H Carry =1Logical Instructions of 8051 uC Y Logic AND instructions Y Logic XOR instructions _ANL—tt will perform logle AND in between two 8 bits numbers. C1 XRL— It will perform logic XOR In between two 8 bits numbers. ANLA,#50H =; A AANDSOH XRLA, #50H A— AXOR SOH ANLA, RL jA© AANDRI XRLA, RI jA@ AXORRL ANLA, 17H 3A AAND [17H] XRLA, 17H A AXOR [17H] ANLA, @R1 A+ AAND [RI] XRLA, @R1 3A AXOR[R1] ANL25H, A 3 [25H] — [25H] AND A XRL25H, A 3 [25H] [25H] XOR A ANL25H, #50H —; [25H] [25H] AND SOH XRL25H,#50H —; [25H] - [25H] XOR SOH Y Logic OR instructions Y Other Logical instructions ORL It will perform logic OR in between two 8 bits numbers. CPL A ~ It will perform 1's compliment of A, meant NOT ORLA,#50H =; A“ AORSOH operation of A. ORLA, RI ;A+AORRL CUR A- It will Clear Accumulator. So A = 00H after instruction, ORLA, 17H 3A~ AOR [17H] swap A ~ It will swap lower Nibble and higher nibble of A, ORLA, @R1 A= AOR[RI] means if A= 78H after instruction A= 87H. ORL 25H, A [25H] [25H] ORA NOP ~ It will do nothing, itis used to generate delay only. NOP ORL 25H, #50H —_; [25H] — [25H] OR SOH ‘means No Operation performed.Rotate Instructions of 8051 uC Y Rotate without Carry instructions G_RRA-Itwill perform rotate Right of A without carry by 1 bit. O iinitially A = 46H & Carry =1. Carry After instruction Ea Inno mEE Carry D After instruction, A = 23H and Carry = 0 _RLA™~Itwill perform rotate Left of A without carry by 1 bit. G Minitially A = 46H & Carry = 1 CACHE DnnDnoOnno D After instruction EE HBDDDREoo Carry After instruction, A = 8CH and Carry =0 ¥ Rotate with Carry instructions RRC A= It will perform rotate Right of A with carry by 1 bit. initially A= 46H & carry =1 = -DHD0 Carry O After Instruction EE BDEDOOEE Carry After instruction, A = A3H and Carry =0 2 ALCA~ It will perform rotate Left of A with carry by 1 bit. O Winitiatly A= 46H & Carry = (a ED Car O After Instruction EH HBDDDBEDE Carry After instruction, A= 8DH and Carry =0Boolean Instructions of 8051 C Y Set, Clear & Complement Carry instructions Y Lo; SETS C-Itwill make Carry Flag =1 D_CURC=It will make Carry Flag =0 OQ CPLC-It will Complement Carry Flag. Y Set, Clear & Complement Bit instructions 2 SETB —tt will make given bit = Logie ‘1 SETB PO.2 5PO.2—1 SETB O7H 3 07H bit location in RAM = 2 OAR Ie will make given bit = Logic 0" CLR PO.2 ;P0.2-0 CLR O7H 3 07H bit location in RAM 0 © CPL ~It will make given bit = complement of initial value CPL PO.2 }PO.2 will get complemented cPLO7H 3 07H bit location in RAM will get complemented Y Move Bit instructions MOV C,P0.2 3 Carry Flag ~ PO.2 MOV PO.2,C 5 PO.2 « Carry Flag Mov 07H,c 3 [07H] bit in RAM < Carry Flag AND & OR Bit instructions QO ANLC, b ~It will do logic AND between Carry flag and bit b and result willbe stored into Carry flag. ANIL C,PO.2 7 — CAND PO.2 ANLC,07H + — CAND [07H] bit in RAM. © ANLC, /b = It will do logic AND between Carry flag and complemented bit b and result will be stored into Carry flag. ANLC,/P0.2 7 C — CAND {NOT} PO.2 ANLC,/07H ; © — CAND {NOT} [07H] bit in RAM OG ORLC, b — It will do logic OR between Carry flag and bit b and result willbe stored into Carry flag. ORL C,PO.2 + C—CORPO.2 ‘ORL.C,07H 3; C— COR [07H] bit in RAM. ORL C, /b — It will do logic OR between Carry flag and complemented bit b and result will be stored into Carry flag ORL C,/PO.2 COR {NOT) PO.2 ORL C,/07H 3 — COR {NOI} [07H] bit in RAMData Transfer Instructions of 8051 uC Y Move instructions Y Stack instructions 2 MOV- twill move data from one location to another location. 1 PUSH ~It will store data on stack MOVA,#50H =; Ax SOH In PUSH, 1" SP will increment by 1, then it will store data on stack. MOV A, RL jACRL POP tt will load data from stack MOVA,SOH =; A~- [50H] Dim PoP, 4" load data from stack, then it will decrement SP by 2. MOVA,@R1 = ;A~[RI] PUSH RI 1 will be stored on stack MOV RI, A pRLOA PUSH 25H 3 [25H] will be stored on stack MOVR1,#50H = ;R1~SOH POP RI ; R1 will be loaded from stack MOVR1,50H RL [SOH] POP 25H [25H] will be loaded from stack MOVSOH, RL 5 [SH] RL Y Exchange instructions MOV SOH, 40H —_; [SOH] ~ [40H] _XCH~tt will exchange the mentioned two data. MOV SOH, @R1_— ; [SOH] = [RI] Wovenia, fala mon toe MOV @R1,#25H_ ;[R1] 25H ante pial MOV @R1, 25H; [Ri] «- [25H] 7 ; MOV DPTR,#2525H; DPTR «- 2525H XCHD A, @Rx ~ It will exchange lower Nibble of the mentioned MOVXA,@R1 —_; A+ [00-R1] from External RAM ‘two data. MOVX A, @DPTR ; A= [DPTR] from External RAM XCHDA,@R1_ =; Ax-~ [R11] only Lower Nibble. MOVX @R1,A —_; [00-R1] ~ A for External RAM. MOVX @DPTR, A; [DPTR] «~ A for External RAM. MOVC A,@A+DPTR; A ~ [A+DPTR] for ROM MOVCA,@A+PC ; A [A+PC] for ROMenn Name Syntax Rang Size Address calculation Instructions Usage Brach Operations of 8051 uC {SJMP, AJMP & LJMP} or ‘SIMP —Short Jump ‘SIMP Label -128 to +127 locations, because of Labell is 8 bits signed No. 2 Bytes {1 Opcode + 1 Label} PC=PC of Next instruction + Label sIMP All conditional Jump available Generally, we use it in same program jump with many conditions and unconditional Ei AIMP ~ Absolute Jump AJIMP Label2 2 Bytes {1 Opcode + 1 Label) PC=1"5 bits same of PC + Bbits of AMP + 8 bits of Label2 AMP ACALL ‘We use it for jump within same page of 2KB. G4Kb is bisected into 32 pages of 2KB ir UMP Long Jump UMP Label3 ‘Maximum range Is 64KB. 3 Bytes {1 Opcode + 2 Label} PC= 16 bits Label3, UMP LCALL We use it to jump anywhere in 64KB of 8051 xc.JMP and CALL of 8051 uC Main peqerre LCALL LabelJMP and CALL of 8051 uC Program Program | PCe Lt UMP L1 ===> 11: Address Physical ~—> Address of Next instruction in PC. pop pC; PAon PC RET | PUSH PC ; PA on stack PCe LL LCALLL1 ————ep> L1: AddressTimer & Counter of 8051 jC 1D 8051 has Two 16 bits Timers TO & T1, working as up counters. TO and T1 is further divided into Bbits of registers THO-TLO and THL-TU, Lh THO Tlo a ra THL Tm © How to Load Count? O This Timers are Up counter. O 50, on given clock it will increment by 3. 1 When it reaches to FFFFH, it will rolls back to O000H and during that it will generates Timer Overflow interrupt. Count = FFFFH ~ Value +1 So, if you wants to count 9 then Count = FFFF—9 += FFF7H MOV THO, #EFH MoV Lo, #E7H Clock COUNT 1 This count loaded in T0 oF 71 will increment after every clock. Gi Timer or Counter? 1G If clock to the count is given by internal clock of 8051 then it will be timer and if clock is given by external clock on TO and T1 then it will counter. That is to be configured by TMOD register of 8051. QD 1/c bit will decide timer or counter configuration of 8051. How Timer / Counter works? Load Count in T0 or T1 Make TFO or TF1 bit pn adres ‘Count will ‘to 0 before it jumps increase after | to 1sR Address every clock When Count rolls from FFFFH to 0000H, it will make TFO or TEI bit to 1. {It is interrupt to 8051} RETI ISR Address of Timer 0 and Timer 1 Timer 0 ISR Address is OOOBH and Timer 1 1SR Address is 001BHTCON & TMOD of 8051 jC 1D 8051 has Two 16 bits Timers TO & T1, working as up counters. ()_IT1 and ITO~ External Interrupt Type bit TO and T1 is further divided into Bbits of registers THO-TLO and O SeT1= INT and INTO must be -ve edge trigger. THL-TL. O Clear0= INT and INTO must be low level trigger. Q 170 & T1 counts internal clock pulses, then itis timer. 170.814 counts External clock pulses, then its Counter. Logie 4 Q Timer action is controlled by TCON and TMOD registers. Y TCON register — {Bit Address TCON.7 to TCON.0} Tri | Tro | TRO | 11 171 1E0 170 Q_ TF1 and TFO- Timer Overflow Flag. / x SET 1= When timer 1 and timer 0 overflows, when timer roll owen oatOs “Ve edge = Logic Clear 0 = When processor executes ISR after overflow. {For i easier Set Case oa ware creas +tviqacn soos 39 TRI and TRO- Timer Run Control Bit OQ SET1 = Start Counting Timer. D Clear o= Halts Timer. — Q tet and 1£0 External interrupt bit SET = when 8051 receives interrupt on INTI and INTO. © Clear 0 = when ISR executed. (For INTT ISR address is 0013 and INTO ISR address 's 0003H)TCON & TMOD of 8051 pC D 8051 has Two 16 bits Timers TO & T1, working as up counters. C)_IT1 and ITO~ External Interrupt Type bit ‘TO and 71 is further divided into Bbits of registers THO-TLO and ) SET 1= INT and INTO must be -ve edge trigger. TLL. G1 Clear 0= INT and INTO must be low level trigger. © I 70.& 71 counts internal clock pulses, then its timer. v — ‘i 1 1870 8.11 counts External clock pulses, then it is Counter. MOD resister jimer Mode Control registes O Timer action is controlled by TON and TMOD registers. Ga oe ee Y TCON register — {Bit Address TCON.7 to TCON.0} C/T -Counter / Timer Type bit ‘SET 1 = Acts as Counter. {External Frequency on T1 & TO} Clear 0 = Acts as Timer. {Internal Frequency Fosc/12) tri | Tro | TRO | 1e1 | 1 Eo ‘Fi and TFO ~ Timer Overflow Flag SET 1 = When timer 1 and timer 0 overflows, when timer roll overs toall o's. Clear 0 = When processor executes ISR after overflow. {For Timer 1 ISR address 's 0O1BH and Timer 0 ISR address Is 000BH) oo GATE ~ Gate Enable Control bit SET 1 = Timer Controlled by Hardware. {INTX Signal} Clear 0= Timer independent on INTX signal. o © ooo ooo Q TRI and TRO~ Timer Run Contro! Bit Ke Mode Control Bs Sera « star counting Timer. DD Clear 0= Halts Timer. Oulno Timer Mode 0 G11 and 1£0—External interrupt bit o 4 Timer Mode 1 _SET1 = when 8051 receives interrupt on INTI and INTO. ne ae Clear 0 = when ISR executed. (For INTT ISR address is 0013 and INTO ISR address is 0003H) 2 Timer Mode 3Working of Timer/Counter in 8051 uC ¥_TMOD register - Timer Mode Control register Ei mo | Gare} c/T | mi] Mo Timer 1 Timer 0 Step-4.- Load Count im THO-TLO os ¥ TCON register — {Bit Address TCON.7 to TCON..0} ow rr m7Working of Timer/Counter in 8051 uC ¥ TCON register — {Bit Address TCON.7 to TCON.0} Oscillator fectiue? ¥_TMOD register —Timer Mode Controlregister_§ “| C/T'=0, Timer Mo care] C/T | ma | mo | Gate) c/T | mi ar Timer 1 Timer 0 TO orT1 Pin 8051 has Two 16 bits Timers TO & T1, working as up counters. By C/T bit we can select timer and counter. —_-_-_————- tn Timer, clock will be given by internal clock. {In counter, clock will be given by TO or T1 Pin of 8051. Counter To have running counter, TR bit of TCON register must be 1. If Timer/Counter is triggered by external signal then GATE = 1 of TOMD register, which means Timer/ Counter operation will get trigger by INTX {INTO or INT}. Mf Timer 0 Is configured then with GATE bit we use INTO ipyty hardware interrupt to trigger Timer/Counter. OO if Timer 1 1s configured then with GATE bit we use INTL hardware interrupt to trigger Timer/Counter. GATE OO IEGATE bit is logic 2, then INTX pin will used for timer/Counter only. ee ee Count Stages C/T =1, Counter cooooo TRO or TR1 oModes of Timer/Counter in 8051 uC Y Timer Mode 0 {13 bits Timer/ Counter} eo” ee TUX has 5 bits for count and THX has 8 bits for count. So in total, 13 bits of count is available in this mode 0. After 32 counts TLX rolls over and it will increment THX. So TUX will divides the frequency by 32. By this mode, total maximum count can be 2'%= 8} ‘So maximum delay = 8192 (12/Fosc) v Timer Mode 1 {16 bits Timer/ Counter} Interrupt Clock_ aro boat) TEX P Q TLX and THX used completely here with Mode 1. © On each clock 16 bits will increment by 1. © TFX will set to 2, when all 16 bits rolls from FFFFH to 0000H. Q By this mode, total maximum count can be 2"¢= 64K, G1 So maximum delay = 65536 (12/Fose) oooo oO v Timer Mode 2 {8 Auto reload TL from TH} Clock, Interrupt hd) ] Bhat) Q TLXxwill increment on every count. Q When TLX rolls over from FFH to 00H, ‘Two events are happening. 1. TEX will give interrupt 2. THX will reload TX Maximum count = 2"=256 Maximum delay = 256 (12/Fose) ¥ Timer Mode 3 {Two 8 bits timer by Timer 0} Interruy © T1oand THO used with two separate timers. © TLowill give interrupt to TFO flag bit of Timer 0. G T1Ocan be used as Timer and Counter. © THO will give ipterrupt to TFS flag bit of Timer 1. Q THO can only be used as Timer.Timer Programming in 8051 uC O Write a program to Generate delay of 20 uSec and ¥_TMOD register ~ Timer Mode Control register send logic 1 on P2.0. Assume Fosc = 12MHz Coal De To v\ THo TLO <8 hits vogitery Ts Y™ TH, The ol 8 bite regithey ¥ TCON register ~ {Bit Address TCON.7 to TCON.0} Timor OverHeo Lit of (hoe on BaslyTimer Programming in 8051 uC C write a program to Generate delay of 20 uSec and send logic 1 on P2.0, Assume Fosc = 12MHz ¥ TCON register — {Bit Address TCON.7 to TCON.0} tri | tri | tro | TRO | 11 | 11 | 160 | 170 ¥ TMOD register —Timer Mode Control register Wait: i oe Oe el Timer timer toe: For Timer 0 with Mode 1 as 16 bits timer, TMOD = 0000 00018 G To start Timer 0 with mode 1, TCON = 0001 00008 1D Tostop time 0 with mode 1, TON = 0000 00008 Tocalculate Count, one count time = 12/Fose = 1ySec. Sovalue of Count = 20= 14H © Astimer is up counter actual value should be loaded will be ‘Count = FFFFH~14H + 1 = FFECH © T= ECH and THO = FFH, to be loaded for delay of 20nSec. MoV TMoD, #000000018 MOV 'TLO, HECH MOV THO, #FFH MOV TCON, #000100008 JNB TCON.S, Wait SETB P2.0 MOV TCON, #000000008 SIMP Here sTimer 0 Mode 1 jCount 20 = 14H ;Start Timer jwait for 20nSec jlogie ‘1’ on P2.0 Stop Timer End of ProgramC write a program to Generate square wave of 1KHz ¥ TCON register — {Bit Address TCON.7 to TCON.0} v TMOD register Timer Programming in 8051 C on TxD pin. Assume Fosc = 12MHz tri | tri | tro | tro | 161 | 111 | 160 | tro Timer Mode Control register Gate| c/T | mi | mo | Gate| c/T | mi | Mo a o ooo oouoo imer 1 Timer 0 For Timer 0 with Mode 2 as 16 bits timer, TMOD = 0000 00018 To start Timer 0 with mode 1, TCON = 0001 0000B To stop time 0 with mode 1, TCON = 0000 00008 Square wave of 1KHz has time = Amsec. So for 0.5msec, It should be high and for 0.5msec, it should be low. ‘To calculate Count, one count time = 12/Fose = 1ySec. So value of Count = 0.Smsec/1pSec = 500 = 1F4H. As timer is up counter actual value should be loaded will be ‘Count = FFFFH ~1F4H + 1= FEOCH TLO= OCH and THO = FEH Repeat: Wait: CLR 3.1 MOV TMOD, #000000018 MOV TLO, HOCH MOV THO, HFEH MOV TCON, #0100008 JNB TCON.5, Wait CPL P3.1 Mov TCON, #000000008 SIMP Repgat iClear TxD line ;Timer 0 Mode 1 sCount 500 = 1F4H Start Timer jwait for 0.5mSec iSquare wave ;Stop Timer sRepeat of ProgramSerial Communication in 8051 uCSerial Communication in 8051 uC 8051 Microcontroller o o For Serial Communication, 8051 has two pins: TxD (P3.1) for serial transmission and RxD {P3.0} for serial reception. SBUF register {8 bits) will give and take data serially for serial communication on TxD and RxD. In serial communication, 1 it will send/receive MSB. Once, 1Byte transmission is completed, Ti interrupt tells processor 8 bits transmission is completed. Once, 1Byte Reception is completed, Ri interrupt tells processor 8 bits reception is completed. I send/receive LSB and at last — ISR Program Interrupt 17 < | al ‘SBUF, A CLR Ti 7. ISR Program Lene LZ < | ~™N MOV A, SBUF CLR Ri To configure serial communication, we need to configure SCON register of 8051.SCON Register i in 8051 uC ¥ SCON Serial Control ret {Bit Address SCON.7 to SCON.0} are a 2 SMO & SM1- Mode Control bits Es Mode 0 Shift Register Fose/12 o 1 Mode 1 BS bItUART Variable 1 oO Mode 2 9 bit UART Fosc/32 or Fosc/64 een tens reat Mode 0 {shift Register sends only data) Hn Mode 4 (8 Bit UART, 1* Start bit 0, then Sits data and at last stop bit 1) BDO Mode 2 & 3 {9 Bit UART, 1" Start bit 0, then 8 bits data, 1 bit parity and at last stop bit 1) HORS ooo coo ooo Gooo oooo ‘SM2~ Enables Multiprocessor System with Mode 2 and Mode 3. REN ~ Receiver Enable REN = 0, receiver disabled REN = 1, receiver enabled ‘TBS ~ Transmitted bit 8 {Technically itis programmable 9* bit in mode 2 and 3} Mode 0~not used Mode 1 ~ stop bit ‘1’ Mode 2 & 3 ~ Parity bit, programmed by programmer. RBS — Received bit 8 {Technically it is programmable 9" bit in mode 2 and 3) Mode 0~ not used Mode 1 - stop bit ‘1” Mode 2 & 3 ~ Parity bit, programmed by programmer. I~ Receive Interrupt twill be one after SBUF receives 8 bits data. Iwill be cleared by programmer in ISR program. Ti Transmit Interrupt {twill be one after SBUF transmits 8 bits data. ‘Tiwill be cleared by programmer in ISR program.RS 232 Protocol ‘ Basics of RS 232 Protocol ‘in Details of DB9 and DB25 connector © RS 232 protocols used for serial communication. ta3a5 Ties oy? (RS 232 protocol provides Asynchronous full duplex SLE ‘communication, (Without Clock} B OOOO HUE), RS 232 protocol can handle serial communication with the distance of Soft, depending on cable type and bit rate. Wie hh oh and ads ORS 232 protocol can handle maximum data rate of IMbps. el need 1 Aswe nrease the length of able apactance wil abe vcrease ESSE EESTI IESTIEES [ee ICE ES which will limits the data rate. cseaall camer 1D Some special cables are also available, by which we can have a 8 cD (DCE oa ‘communication up to 130fts. 2 3 RK —DCE_—ate_——_Receive Data AS 232 protest uses DBP or D825 connector for srl 5 SWE Ea Mores ea Een oa © In DB25 connector, only Nine lines are used as it Is there with 4g. 20. -DTR —dDTE_— Control. -—Data Terminal Bo, Ready + Connectors of RS 232 Protocol 5 Fil ESCH es = SinalGround } 6 6 DSR DCE Control Data Set Ready 7 4 RTS. TE Control Request to Send 8 5 CTS. DCE Control. CleartoSend 9 22 RE_—DLE_— Control Ringindiator - Rest None = - : -RS 232 Protocol DTE and DCE of RS 232 Protocol 1D DTE~ Data Terminal Equipment. {Computer} 1D DCE - Data Communication Equipment. (Modem) D._ Communication happens between DTE and DCE, we can not have ‘communication between two OTE or two DCE. O For two DTE communication, we use Null modem in between two OTE for communication. Daa Soe DCE conta 1 8 Carter Detect 2 RX DCE_—Data_—Reeelve Data 3 TK —_DTE— Osta Transmit Data 4 20 © -DTR —DTE_— Control. Data Terminal Ready 5 7 86 : = Signal Ground 6 6 DSR DCE Control Data Set Ready 7 4 RTS —DTE Control Request toSend 8 S CTS. DCE Control Clear toSend 9 22° RL DCE Control__—_—Rng ndcator > Rest. None - : B * Voltages of RS 232 Protocol roy Logic 0 pr sv. 3V Tx Side |------- 0 Voltage- -| Rx Side 3V [-] Logic’ [65Y + Handshaking of RS 232 Protocol 1 RTS of DTE is connected with CTS of DCE and visa versa. 1 DSR of OTE is connected with OTR of OCE and visa versa. O Teof DTE is connected with Rx of OCE and visa versa. 1D 56 of OTE and DCE is commonly connected. Q 2" OTE is giving RTS {Request to Send) Signal to DCE. 1 I DCE is not busy then only DCE sends respond on DTR (Data ‘Transmit Ready) Then OTE can send data to OCE.RS 232 Protocol ‘+ Data Frame Format of RS 232 Protocol 4+ RS 232 Protocol in Embedded System Data Frame Format of RS 232 Protocols similar to UART. Majority of embedded system work with voltage range of Oto SV and RS 232 works with #15V. | Data {@ bits} CET IN 2 To make data transfer compactible, we need to use MAX 232 IC EISNMEISSEU) with embedded system to enable RS 232 Protocol. Q_MAX 232 converts voltage range of (0-SV) into #25V and visa 2 In one frame of RS 232 Protocol, along with 8 bits of data, start bit, stop bit and parity redundancy is also added. ey Parity bit is optional but it can be used to identify the error in ee eee nar re rest rotocol. data reception. MAX 232 Board Typical Embedded System DTEInterrupts in 8051 uC + Basics of Interrupts in 8051 8051 has five interrupts and all are vectored interrupt. Two Hardware interrupts: INTO and INTE Two Timer Overflow internal interrupts :TFO and TF D Serial Communication internal interrupt: Common for RI and TL © Allthe interrupts are controlled by IE and IP registers. a ISR Program PUSH PC wd pm + Priority and Vector Address of Interrupts in 8051 ea fod eee 18TO 1 (0003H Tro 2 ‘0008 INTT 0013H Tr 4 oo18H Serial (Ri or TI) 5 (00234 *h IE~ Interrupt Enable Register (Bit Addressable IE.7 to IE.0} Nae ew 2 EA-Enable All, ET2 — Reserved, ES ~ Enable Serial, ET1 - Enable Timer 1, EX1 — Enable INTH, ETO — Enable Timer 0 and EXO — Enable INTO. © To Enable it, make it 1 OF ToDisable it, make it 0 sh IP — Interrupt Priority Register (Bit Addressable IP.7 to 1P.0} E ee ena PT2— Reserved, PS ~ Priority Serial, PT ~ Priority Timer 1, PX1 — Priority INT1, PTO — Priority Timer 0 and PXO— Priority INTO. To have high Priority, make it 1 OF Tohave low Priority, make itPower Saving Modes in 8051 iC + Basics of Power Saving in 8051 8051 has two power saving modes: 1. Idle Mode 2. Power Down Mode This power saving modes are controlled by PCON register. ++ Advantages of Power Saving in 8051 8051 is used in embedded systems operated with battery, So it saves cost of system No need of fans and cooling system due to this modes. Ott makes circuit compact, as we don’t need additional circuits for cooling. 0 itwill increase ti & reliability of entire system. * PCON — Power Control Register {No bit addressable} BY Eee ‘SMOD ~ Serial Baud rate. GF1 & GFO- General Purpose, left for user to define it. PD ~ Power Down Mode. If PO = 1, Power Down Mode Is ON If PO = 0, Power Down Mode Is OFF IDL - Power Idle Mode. HIDL= 1, Idle Mode is ON IDL = 0, Idle Mode is OFF ooo oooog ‘+ Note: f PD and IDL, both are enabled by keeping them 1, then £8051 will consider PD Mode only. + Idle Mode of Power Saving in 8051 PCON is not bit addressable register, so to turn ON Idle Mode, we can use ORL 87H, #OIH {87H is Address of PCON register) In idle Mode, Clock to CPU is Cut OFF, Hence CPU will go in Sleep Mode. Because of It, we almost saves 80% of power supplied to 8052 microcontroller. In idle Mode, Clock is available to other On chip components like RAM, Timer, Ports, PC, SP, PSW etc. By Interrupt and RESET, we can terminate Idle Mode. After RESET, we can not regain original state of Controller Power Down Mode of Power Saving in 8051 PCON is not bit addressable register, so to turn ON Power Down Mode, we can use ORL 87H, H02H (87H is Address of PCON register} In Power Down Mode, Clock to entire 8051 is Cut OFF. In this mode we save maximum Power. 1 By RESET only, we can terminate Power Down Mode. ° O+o00 0 oc oaPower Saving in 8051 uC | HH XLAT2 XUATL ince To Timer, RAM, lO Ports ete. PDMemory Interfacing in 8051 uC O Design following system with 8051 microcontroller. | = X®!PROM wing 2x8 ¢PnoM 2. 8051 working in 122MHz. il agen natn oneicameat . ie 7 Addr for 2KB Addeess = 2'° x 2! = 241 2. 4KB EPROM using 2KB EPROM ‘So it needs 11 address lines. 3. 8KB RAM using 4KB RAM Data Lines for 2XB = 8 [For Byte, itis 8 bits] In Memory interfacing, we need to interface four Scodtol Line for EPROM = Memory Reed (REEN. Fer 9951 ROM dete reed) categories of lines: {KB RAM using 4KB RAM Numbers of Chips = 2 chips of 4K8 RAM & Address Unes for KB Address = 2" 2? = 247 + Data Lines Soit needs 12 address ines. = Control Lines KB =8 For Byte, itis bits] = + Chip Select Control ines for 4KB RAM = Memory Read RD & Memory White IVR for RAM of 8051. [PROM 1 o Oe HOM WOn Fon Te Kon TON Kon hes ko) 1000H 2KB : 1 1 1 1 1 1 11 11 17FFH ‘EPROM 2 o o o 0 0 o o 0 0 o 0 1800H — 1 1 1 a 1 1 1 11 11 1FFFH RAMI o o On EORTO o o 0 0 oo 0000H axe 1 1 1 1 1 1 1 aoa ao. OFFFH RAM 25, o o o o 0 o o 0 0 o 0 1000H = 1 1 1 1 1 1 1 11 a1 1FFFH Can be used for Chip SelectP2{AB-AIS}|Delay calculation for 0.5 sec delay Here 8051 Crystal Frequency is 12MHz. So, clock frequency is 12MHz/12 = 1MHz So, Time period of 1 clock = ips DJNZ will take 2 Machine cycles. So, for 0.5 sec delay 2x1psxN=0.5 N = 250000 = 250 x250 x 4 R3 = 250 R4=250 R5=4MOV A,#00H MOV P2,A Mov A,#00H LS BACK: MOV P2,A) ALL DELAY PLA SIMP BACK DELAY: MOV R5,#4 H3: MOV R4,#250 H2: MOV R3,#250 Hi: DINZ R3,H1 DINZ R4,H2 DINZ R5,H3 RET END S //Make P2 as an output port //Complement Accumulator //For generating 0.5sec delay for 12MHz crystal frequency 1/2 MC for 8051AGAIN:! SETB.PLO ACALL DELAY LR P1.0 ACALL DELAY SJMP AGAIN DELAY: H3: H2: Hi: MOV R5,#4 MOV R4,#250 MOV R3,#250 * DJNZ R3,H1 DINZ R4,H2 DJNZ R5,H3 ET END {set only P1.0 Helear only P1.0 A CQ G //For generating 0.Ssec delay for 12MHz crystal frequency H/2MC for 8051