LTM4671

Quad DC/DC µModule Regulator with

Configurable Dual 12A, Dual 5A Output Array

FEATURES DESCRIPTION
n Quad Output Step-Down µModule® Regulator with The LTM®4671 is a quad DC/DC step-down µModule
Dual 12A and Dual 5A Output (micromodule) regulator offering dual 12A and dual 5A
n Wide Input Voltage Range: 3.1V to 20V output. Included in the package are the switching control-
n Dual 12A DC Output from 0.6V to 3.3V lers, power FETs, inductors and support components.
n Dual 5A DC Output from 0.6V to 5.5V Operating over an input voltage range of 3.1V to 20V, the
n Up to 7W Power Dissipation (TA = 60°C, 200LFM, LTM4671 supports an output voltage range of 0.6V to
No Heat Sink) 3.3V for two 12A channels and 0.6V to 5.5V for two 5A
n ±1.5% Total Output Voltage Regulation channels, each set by a single external resistor. Only bulk
n Dual Differential Sensing Amplifier input and output capacitors are needed.
n Current Mode Control, Fast Transient Response
n Parallelable for Higher Output Current Fault protection features include overvoltage, overcurrent
n Selectable Burst Mode® Operation and overtemperature protection. The LTM4671 is offered
n Output Voltage Tracking in 9.5mm × 16mm × 4.72mm BGA package.
n Internal Temperature Sensing Diode Output Configurable Output Array*
n External Frequency Synchronization 12A 12A
24A 24A
n Overvoltage, Current and Temperature Protection 12A 12A
n 9.5mm × 16mm × 4.72mm BGA Package 5A 5A
10A 10A
5A 5A

APPLICATIONS * Note 4

n Multirail Point-of-Load Regulation All registered trademarks and trademarks are the property of their respective owners.

n FPGAs, DSPs and ASICs Applications

TYPICAL APPLICATION
4V to 20V Input, 12A, 12A, 5A, 5A DC/DC Step-Down µModule Regulator 12VIN Efficiency vs Load Current
VIN VOUT0 100
VIN VOUT0
5V TO 20V CIN VOSNS0+ COUT0 1.2V/12A
SVIN0 100µF ×4
22µF SVIN3 VOSNS0– 95
×2 60.4k
RUN0 FB0
RUN1 90
VOUT1 VOUT1
EFFICIENCY (%)

RUN2
RUN3 VOSNS1+ COUT1 2.5V/5A
19.1k
COMP0a FB1 47µF 85
COMP0b
LTM4671 VOUT2 VOUT2
COMP1 VOSNS2+ 80
COUT2 3.3V/5A
COMP2 13.3k
FB2 47µF VOUT = 1.0
COMP3a VOUT = 1.2
75
COMP3b VOUT3 VOUT = 2.5
VOUT3
TRACK/SS0 VOSNS3+ COUT3 1.0V/12A VOUT = 3.3
0.1μF TRACK/SS1 VOSNS3– 100µF ×4 70
TRACK/SS2 90.9k 0 2 4 6 8 10 12
0.1μF FB3
0.1μF TRACK/SS3 LOAD CURRENT (A)
4671 TA01b
0.1μF TMON GND
4671 TA01a

Rev. B

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LTM4671
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1) (See Pin Functions, Component BGA Pinout Table)
VIN, SVIN0, SVIN3......................................... –0.3V to 22V
VOUT0, VOUT3.............................................. –0.3V to 3.6V TOP VIEW
TSENSE0– TSENSE0+
VOUT1, VOUT2................................................. –0.3V to 6V A

INTVCC0, INTVCC12, INTVCC3,.................... –0.3V to 3.6V

FREQ0, FREQ12, FREQ3,............................ –0.3V to 3.6V
B

VOUT0
FB0, FB1, FB2, FB3,.................................... –0.3V to 3.6V C

COMP0a, COMP0b, COMP3a, COMP3b,

COMP1, COMP2,.................................... –0.3V to 3.6V D

VIN
RUN0, RUN1, RUN2, RUN3......................... –0.3V to 22V
GND PHMODE0 INTVCC0 SVIN0 CLKOUT0 PGOOD0
E

TRACK/SS0, TRACK/SS1, TRACK/SS2, VOSNS0– TRACK/SS0 FREQ0 RUN0

TRACK/SS3,.......................................... –0.3V to 3.6V F

GND GND
MODE/
TRACK/SS1 VOSNS0+
PGOOD0, PGOOD1, PGOOD2, PGOOD3,.... –0.3V to 3.6V G
FB0 GND CLKIN0

VOSNS0+, VOSNS0 –, VOSNS3+, PGOOD1 FB1 COMP0a COMP0b

VOSNS3–,.............................................. –0.3V to 3.6V H

VOUT1 GND GND
VOSNS1, VOSNS2......................................... –0.3V to 6V
RUN1 VOSNS1 COMP1
J VIN

TSENSE0+, TSENSE0 –, TSENSE3+, TMON INTVCC12 FREQ12

TSENSE3–.............................................. –0.3V to 0.8V K GND GND

MODE/
GND
TMON........................................................ –0.3V to 3.6V
GND RUN2 CLKIN12 VOSNS2
L

MODE/CLKIN0, CLKOUT0, MODE/CLKIN3, VOUT2

VIN
PGOOD2 FB2 GND COMP2

CLKOUT3, MODE/CLKIN12.................... –0.3V to 3.6V M

TRACK/

Operating Junction Temperature (Note 2).–40°C to 125°C N

SS2 COMP3b COMP3a FB3 VOSNS3+

Storage Temperature Range................... –55°C to 125°C GND GND CLKOUT3 RUN3 FREQ3
TRACK/
SS3 VOSNS3– GND

Peak Solder Reflow Body Temperature.................. 245°C P

MODE/
PHMODE3 PGOOD3 CLKIN3 SVIN3 INTVCC3
R
VIN

VOUT3 GND
U

GND
V

TSENSE3+ TSENSE3– GND

W

1 2 3 4 5 6 7 8 9 10 11

BGA PACKAGE
209-LEAD (9.5mm × 16mm × 4.72mm)
TJMAX = 125°C, θJCTOP = 12.8°C/W, θJCBOTTOM = 1.5°C/W, θJA = 12°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT: 1.94g

Rev. B

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 LTM4671
ORDER INFORMATION
PART MARKING* PACKAGE MSL TEMPERATURE RANGE
PART NUMBER PAD OR BALL FINISH DEVICE FINISH CODE TYPE RATING (SEE NOTE 2)
LTM4671EY#PBF LTM4671Y
SAC305 (RoHS) e1 BGA 3 –40°C to 125°C
LTM4671IY#PBF LTM4671Y
• Device temperature grade is indicated by a label on the shipping container. • This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
to Recommended BGA PCB Assembly and Manufacturing
• BGA Package and Tray Drawings Procedures.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Section: (12A Channels)
VIN Input DC Voltage l 3.1 20 V
VIN(AFTER START-UP) Input DC Voltage After Start-Up l 2.9 20 V
VOUT(RANGE) Output Voltage Range l 0.6 3.3 V
VOUT(DC) Output Voltage, Total Variation with CIN = 22µF, COUT = 100µF Ceramic l 1.482 1.50 1.518 V
Line and Load RFB = 40.2k, Continuous Current Mode
SVIN = VIN = 3.1V to 20V, IOUT = 0A to 12A
IQ(VIN) Input Supply Bias Current SVIN = VIN = 12V, VOUT = 1.5V, Continuous Current Mode 75 mA
SVIN = VIN = 12V, RUN = 0, Shutdown 70 µA
IS(VIN) Input Supply Current SVIN = VIN = 12V, VOUT = 1.5V, IOUT = 12A 1.6 A
IOUT(DC) Output Continuous Current Range SVIN = VIN = 12V, VOUT = 1.5V (Note 4) 0 12 A
∆VOUT(LINE)/VOUT Line Regulation Accuracy VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A l 0.001 0.05 %/V
∆VOUT(LOAD)/VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 12A l 0.2 0.5 %
%
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic 6 mV
SVIN = VIN = 12V, VOUT = 1.5V
∆VOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, 15 mV
SVIN = VIN = 12V, VOUT = 1.5V
tSTART Turn-On Time TRACK/SS = 0.01µF, 1 ms
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 25% to 0% of Full Load ±50 mV
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
tSETTLE Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load 50 µs
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
IOUTPK Output Current Limit SVIN = VIN = 12V, VOUT = 1.5V 14 A
VFB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V l 0.594 0.6 0.606 V
IFB Current at VFB Pin (Note 6) ±50 nA
RFB(TOP) Resistor Between VOUT and VFB Pins 60.05 60.40 60.75 kΩ

Rev. B

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LTM4671
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VRUN RUN Pin ON Threshold VRUN Rising 1.10 1.20 1.30 V
Hysteresis 150 mV
UVLO Undervoltage Lockout INTVCC Falling 2.4 2.55 2.7 V
Hysteresis 0.4 V
ITRACK/SS Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V 6 µA
tON(MIN) Minimum On-Time (Note 5) 25 ns
tOFF(MIN) Minimum Off-Time (Note 5) 80 ns
VPGOOD PGOOD Trip Level VFB With Respect to Set Output
VFB Ramping Negative –10 –8 –6 %
VFB Ramping Positive 6 8 10 %
RPGOOD PGOOD Pull-Down Resistance 1mA Load 8 15 Ω
INTVCC Internal VCC Voltage 3.2 3.3 3.4 V
FREQ Default Switching Frequency 600 kHz
CLKIN_H CLKIN_H Input High Threshold 1 V
CLKIN_H Input Low Threshold 0.3 V
Switching Regulator Section: (5A Channels)
VIN Input DC Voltage l 3.1 20 V
VIN(AFTER START-UP) Input DC Voltage After Start-Up l 2.9 20 V
VOUT(RANGE) Output Voltage Range l 0.6 5.5 V
VOUT(DC) Output Voltage, Total Variation with CIN = 22µF, COUT = 100µF Ceramic l 1.477 1.50 1.523 V
Line and Load RFB = 40.2k, Continuous Current Mode
VIN = 3.1V to 20V, IOUT = 0A to 5A
IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Continuous Current Mode 18 mA
VIN = 12V, VOUT = 1.5V, Burst Mode Operation (IOUT = 0.5A 82 mA
VIN = 12V, RUN = 0V, Shutdown 75 µA
IS(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 5A 0.7 A
IOUT(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 4) 0 5 A
∆VOUT(LINE)/VOUT Line Regulation Accuracy VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A l 0.001 0.05 %/V
∆VOUT(LOAD)/VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 5A l 0.2 0.5 %
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic 8 mV
VIN = 12V, VOUT = 1.5V
∆VOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, 15 mV
VIN = 12V, VOUT = 1.5V
tSTART Turn-On Time TRACK/SS = 0.01µF, 5 ms
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 25% to 0% of Full Load 30 mV
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
tSETTLE Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load 70 µs
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V 6 A
VFB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V l 0.592 0.6 0.608 V
IFB Current at VFB Pin (Note 6) ±30 nA
RFB(TOP) Resistor Between VOUT and VFB Pins 60.05 60.40 60.75 kΩ
VRUN RUN Pin ON Threshold VRUN Rising 1.15 1.25 1.35 V
Hysteresis 200 mV

Rev. B

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 LTM4671
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
UVLO Undervoltage Lockout INTVCC Falling 2.2 2.4 2.6 V
Hysteresis 0.5 V
ITRACK/SS Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V 1.4 µA
tON(MIN) Minimum On-Time (Note 5) 20 ns
tOFF(MIN) Minimum Off-Time (Note 5) 45 ns
VPGOOD PGOOD Trip Level VFB with Respect to Set Output
VFB Ramping Negative –10 –8 –5 %
VFB Ramping Positive 5 8 10 %
RPGOOD PGOOD Pull-Down Resistance 10mA Load 25 Ω
INTVCC Internal VCC Voltage 3.1 3.3 3.5 V
FREQ Default Switching Frequency 1 MHz
MODE/CLKIN_L MODE/CLKIN_L High Threshold 1 V
MODE/CLKIN_L Low Threshold 0.3 V
TMON12 Temperature Monitor TA = 25°C 1.5 V
Temperature Monitor Slop 200 °C/V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The minimum on-time is tested at wafer sort.
may cause permanent damage to the device. Exposure to any Absolute Note 4: See output current derating curves for different VIN, VOUT and TA.
Maximum Rating condition for extended periods may affect device Note 5: Guaranteed by design.
reliability and lifetime.
Note 6: 100% tested at wafer level.
Note 2: The LTM4671 is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4671E is guaranteed to meet performance
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4671I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.

Rev. B

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LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Dual 12A Channels

Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current

from 3.3VIN from 5VIN from 12VIN
100 100 100

95 95 95

90 90 90

EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)

85 85 85
VOUT = 0.9V VOUT = 0.9V
VOUT = 0.9V 80 VOUT = 1.0V 80 VOUT = 1.0V
80
VOUT = 1.0V VOUT = 1.2V VOUT = 1.2V
VOUT = 1.2V VOUT = 1.5V VOUT = 1.5V
75 VOUT = 1.5V 75 VOUT = 1.8V 75 VOUT = 1.8V
VOUT = 1.8V VOUT = 2.5V VOUT = 2.5V
VOUT = 2.5V VOUT = 3.3V VOUT = 3.3V
70 70 70
0 2 4 6 8 10 12 0 2 4 6 8 10 12 0 2 4 6 8 10 12
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4671 G01 4671 G02 4671 G03

1.0V Output Transient Response 1.2V Output Transient Response 1.5V Output Transient Response

VOUT VOUT VOUT

(AC-COUPLED) (AC-COUPLED) (AC-COUPLED)
50mV/DIV 50mV/DIV 50mV/DIV

LOAD STEP LOAD STEP LOAD STEP

2A/DIV 2A/DIV 2A/DIV

50μs/DIV 4671 G04 50μs/DIV 4671 G05

50μs/DIV 4671 G06

VIN = 12V, VOUT = 1V, fSW = 600kHz VIN = 12V, VOUT = 1.2V, fSW = 600kHz VIN = 12V, VOUT = 1.5V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS COUT = 3× 100μF CERAMIC CAPACITORS COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs 3A (25%) LOAD STEP, 1A/μs 3A (25%) LOAD STEP, 1A/μs

1.8V Output Transient Response 2.5V Output Transient Response 3.3V Output Transient Response

VOUT VOUT VOUT

(AC-COUPLED) (AC-COUPLED) (AC-COUPLED)
50mV/DIV 50mV/DIV 100mV/DIV

LOAD STEP LOAD STEP LOAD STEP

2A/DIV 2A/DIV 2A/DIV

50μs/DIV 4671 G07 50μs/DIV 4671 G08 50μs/DIV 4671 G09

VIN = 12V, VOUT = 1.8V, fSW = 600kHz VIN = 12V, VOUT = 2.5V, fSW = 600kHz VIN = 12V, VOUT = 3.3V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS COUT = 3× 100μF CERAMIC CAPACITORS COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs 3A (25%) LOAD STEP, 1A/μs 3A (25%) LOAD STEP, 1A/μs

Rev. B

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 LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Dual 12A Channels

Start-Up Waveform with No Load Start-Up Waveform with 12A Load Short-Circuit Waveform with No
Current Applied Current Applied Load Current Exist

RUN RUN
10V/DIV 10V/DIV LIN
PGOOD PGOOD 500mA/DIV
5V/DIV 5V/DIV
LIN LIN
200mA/DIV 200mA/DIV
VOUT
VOUT VOUT 500mV/DIV
1V/DIV 1V/DIV

2ms/DIV 4671 G10

2ms/DIV 4671 G11

50μs/DIV 4671 G12

VIN = 12V, VOUT = 1V, fSW = 600kHz VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 1× 330μF POSCAP, COUT = 1× 330μF POSCAP, VIN = 12V, VOUT = 1V, fSW = 600kHz
2× 100μF CERAMIC CAPACITORS 2× 100μF CERAMIC CAPACITORS COUT = 1× 330μF POSCAP,
CSS = 0.1μF CSS = 0.1μF 2× 100μF CERAMIC CAPACITORS

Short-Circuit Waveform with 12A

Load Current Exist Output Ripple Start Into Pre-Biased Output

RUN
10V/DIV
LIN
500mA/DIV PGOOD
5V/DIV
VOUT
(AC-COUPLED) VOUT
10mV/DIV 1V/DIV
VOUT
500mV/DIV LIN
100mA/DIV

50μs/DIV 4671 G13 1μs/DIV 4671 G14 2ms/DIV 4671 G15

VIN = 12V, VOUT = 1V, fSW = 600kHz VIN = 12V, VOUT = 1V, fSW = 600kHz VIN = 12V, VOUT = 1.5V, fSW = 600kHz
COUT = 1× 330μF POSCAP, COUT = 3× 100μF CERAMIC CAPACITORS COUT = 1× 330μF POSCAP +
2× 100μF CERAMIC CAPACITORS 2× 100μF CERAMIC CAPACITORS
VOUT = PREBIASED TO 0.9V

Dual 5A Channels

Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current

from 3.3VIN from 5VIN from 12VIN
100 100 100

95 95 95

90 90 90
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)

85 85 85

80 80 80

75 75 VOUT = 3.3V 75
VOUT = 2.5V VOUT = 2.5V
70 VOUT = 1.8V 70 VOUT = 1.8V 70 VOUT = 5.0V VOUT = 1.5V
VOUT = 1.5V VOUT = 1.5V VOUT = 3.3V VOUT = 1.2V
65 VOUT = 1.2V 65 VOUT = 1.2V 65 VOUT = 2.5V VOUT = 1.0V
VOUT = 1.0V VOUT = 1.0V VOUT = 1.8V
60 60 60
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4671 F16 4671 F17 4671 F18

Rev. B

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LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS

1.0V Output Transient Response 1.2V Output Transient Response 1.5V Output Transient Response

VOUT VOUT VOUT

(AC-COUPLED) (AC-COUPLED) (AC-COUPLED)
50mV/DIV 50mV/DIV 50mV/DIV

LOAD STEP LOAD STEP LOAD STEP

500mA/DIV 500mA/DIV 500mA/DIV

50μs/DIV 4671 G19

50μs/DIV 4671 G20 50μs/DIV 4671 G21

VIN = 12V, VOUT = 1V, fSW = 1MHz VIN = 12V, VOUT = 1.2V, fSW = 1MHz VIN = 12V, VOUT = 1.5V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF CFF = 100pF CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs 1.25A (25%) LOAD STEP, 1A/μs 1.25A (25%) LOAD STEP, 1A/μs

1.8V Output Transient Response 2.5V Output Transient Response 3.3V Output Transient Response

VOUT VOUT VOUT

(AC-COUPLED) (AC-COUPLED) (AC-COUPLED)
50mV/DIV 50mV/DIV 100mV/DIV

LOAD STEP LOAD STEP LOAD STEP

500mA/DIV 500A/DIV 500A/DIV

50μs/DIV 4671 G22

50μs/DIV 4671 G23 50μs/DIV 4671 G24

VIN = 12V, VOUT = 1.8V, fSW = 1MHz VIN = 12V, VOUT = 2.5V, fSW = 1MHz VIN = 12V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF CFF = 100pF CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs 1.25A (25%) LOAD STEP, 1A/μs 1.25A (25%) LOAD STEP, 1A/μs

Start-Up Waveform with No Load Start-Up Waveform with 5A Load

5V Output Transient Response Current Applied Current Applied

RUN RUN
10V/DIV 10V/DIV
VOUT
PGOOD PGOOD
(AC-COUPLED) 5V/DIV 5V/DIV
100mV/DIV
VOUT VOUT
1V/DIV 1V/DIV
LOAD STEP
500A/DIV LIN LIN
200mA/DIV 200mA/DIV

50μs/DIV 4671 G25 20ms/DIV 4671 G26

20ms/DIV 4671 G27

VIN = 12V, VOUT = 1.8V, fSW = 1MHz VIN = 12V, VOUT = 1V, fSW = 1MHz VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF CFF = 100pF, CSS = 0.1μF CFF = 100pF, CSS = 0.1μF
1.25A (25%) LOAD STEP, 1A/μs

Rev. B

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 LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Short-Circuit Waveform with No Short-Circuit Waveform with 5A
Load Current Exist Load Current Exist

LIN
LIN 500mA/DIV
500mA/DIV

VOUT VOUT
500mV/DIV 500mV/DIV

50μs/DIV 4671 G28

50μs/DIV 4671 G29

VIN = 12V, VOUT = 1V, fSW = 1MHz VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF CFF = 100pF

Output Ripple Start Into Pre-Biased Output

RUN
10V/DIV
PGOOD
5V/DIV
LIN
VOUT
5mV/DIV
2V/DIV

LIN
100mA/DIV

500ns/DIV 4671 G30 2ms/DIV 4671 G31

VIN = 12V, VOUT = 1V, fSW = 1MHz VIN = 12V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF CFF = 100pF, VOUT PREBIASED 2V

Rev. B

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LTM4671
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY RUN0 (F11), RUN3 (P7): Run Control Input of Each 12A
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Switching Mode Regulator Channel. Enable regulator
operation by tying the specific RUN pin above 1.2V. Tying
VIN (D7-D11, E8, H6, J5-J6, L5-L6, M6, R10, T7‑T11): it below 1.1V shuts down the specific regulator channel.
Power Input. Pins connect to the drain of the internal top
COMP0a (H10), COMP3a (N9): Current Control Thresh-
MOSFET and Signal VIN to the internal 3.3V regulator for old and Error Amplifier Compensation Point of Each 12A
the control circuitry for each switching mode regulator
Switching Mode Regulator Channel. The internal current
channel. Apply input voltages between these pins and GND
comparator threshold is linearly proportional to this voltage.
pins. Recommend placing input decoupling capacitance Tie the COMPa pins from different channels together for
directly between each of VIN pins and GND pins. parallel operation. The device is internally compensated.
GND (A4-A5, A8-A11, B4-B11, C4-C11, D4-D6, E3-E5, Connect to COMP0b or COMP3b, respectively, to use the
F1-F7, G1-G6, G10, H5, H7, J7, J9, K1-K7, K11, L7, internal compensation. Or connect to a Type-II C-R-C
L11, M5, M7, M10, N1-N6, P1-P5, P11, R3-R5, T4-T6, network to use customized compensation.
U4-U11, V4-V11, W4-W5, W8-W11): Power Ground Pins
COMP0b (H11), COMP3b (N8): Internal Loop Compen-
for Both Input and Output Returns. Use large PCB copper sation Network for Each 12A Switching Mode Regulator
areas to connect all GND together. Channel. Connect to COMP0a or COMP3a, respectively, to
use the internal compensation in majority of applications.
PINS FOR DUAL 12A CHANNELS:
FB0 (G9), FB3 (N10): The Negative Input of the Error
VOUT0 (A1-A3, B1-B3, C1-C3, D1-D3, E1-E2), VOUT3 Amplifier for Each 12A Switching Mode Regulator Channel.
(R1‑R2, T1-T3, U1-U3, V1-V3, W1-W3): Power Output This pin is internally connected to VOSNS0+ or VOSNS3+,
Pins of Each 12A Switching Mode Regulator Channel. respectively, with a 60.4kΩ precision resistor. Output
Apply output load between these pins and GND pins. Rec- voltages can be programmed with an additional resistor
ommend placing output decoupling capacitance directly between FB and VOSNS– pins. In PolyPhase® operation,
between these pins and GND pins. See the Applications tying the FB pins together allows for parallel operation.
Information section for paralleling outputs. See the Applications Information section for details.
PGOOD0 (E11), PGOOD3 (R7): Output Power Good with TRACK/SS0 (F9), TRACK/SS3 (P9): Output Tracking and
Open-Drain Logic of Each 12A Switching Mode Regulator Soft-Start Pin of Each 12A Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage on Channel. Allows the user to control the rise time of the
the FB pin is not within ±10% of the internal 0.6V reference. output voltage. Putting a voltage below 0.6V on this pin
INTVCC0 (E7), INTVCC3 (R11): Internal 3.3V Regulator bypasses the internal reference input to the error ampli-
Output of Each 12A Switching Mode Regulator Channel. fier, instead it servos the FB pin to the TRACK voltage.
The internal power drivers and control circuits are pow- Above 0.6V, the tracking function stops and the internal
ered from this voltage. Decouple each pin to GND with a reference resumes control of the error amplifier. There’s
minimum of 2.2µF local low ESR ceramic capacitor. an internal 6µA pull-up current from INTVCC on this pin,
so putting a capacitor here provides soft-start function.
See the Applications Information section for details.

Rev. B

10 For more information www.analog.com

 LTM4671
PIN FUNCTIONS
FREQ0 (F10), FREQ3 (P8): Switching Frequency Program TSENSE0+ (A7), TSENSE3+ (W6): Temperature Monitor
Pin of Each 12A Switching Mode Regulator Channel. Fre- of Each 12A Switching Mode Regulator Channel. An in-
quency is set internally to 600kHz. An external resistor can ternal diode connected PNP transistor is placed between
be placed from this pin to GND to increase frequency, or TSENSE+ and TSENSE– pins. See the Applications Infor-
from this pin to INTVCC to reduce frequency. See the Ap- mation section.
plications Information section for frequency adjustment.
TSENSE0– (A6), TSENSE3– (W7): Low Side of the Internal
VOSNS0+ (G8), VOSNS3+ (N11): Positive Input to the Dif- Temperature Monitor.
ferential Remote Sense Amplifier of Each 12A Switching
SVIN0 (E9), SVIN3 (R9): Signal VIN. Filtered input voltage
Mode Regulator Channel. Internally, this pin is connected
to the on-chip 3.3V regulator. Tie this pin to the VIN pin in
to VFB with a 60.4k 0.5% precision resistor. See the Ap-
most applications or connect SVIN to an external voltage
plications Information section for details.
supply of at least 4V which must also be greater than VOUT.
VOSNS0– (F8), VOSNS3– (P10): Negative Input to the
Differential Remote Sense Amplifier of Each 12A Switch- PINS FOR DUAL 5A CHANNELS:
ing Mode Regulator Channel. Connect an external resistor
between FB and VOSNS– pin to set the output voltage of VOUT1 (H1-H4, J1-J4), VOUT2 (L1-L4, M1-M4): Power
the specific channel. See the Applications Information Output Pins of Each 5A Switching Mode Regulator Channel.
section for details. Apply output load between these pins and GND pins. Rec-
ommend placing output decoupling capacitance directly
MODE/CLKIN0 (G11), MODE/CLKIN3 (R8): Discontinu- between these pins and GND pins. See the Applications
ous Mode Select Pin and External Synchronization Input Information section for paralleling outputs.
to Phase Detector of Each 12A Switching Mode Regula-
tor Channel. Tie MODE/CLKIN to GND for discontinuous PGOOD1 (H8), PGOOD2 (M8): Output Power Good with
mode of operation. Floating MODE/CLKIN or tying it to Open-Drain Logic of Each 5A Switching Mode Regulator
a voltage above 1V will select forced continuous mode. Channel. PGOOD is pulled to ground when the voltage on
Furthermore, connecting MODE/CLKIN to an external clock the FB pin is not within ±10% of the internal 0.6V reference.
will synchronize the system clock to the external clock and INTVCC12 (K9): Internal 3.3V Regulator Output for Both 5A
puts the part in forced continuous mode. See Applications Switching Mode Regulator Channels. The internal power
Information section for details. drivers and control circuits are powered from this voltage.
CLKOUT0 (E10), CLKOUT3 (P6): Output Clock Signal for Decouple each pin to GND with a minimum of 2.2µF local
PolyPhase Operation of Each 12A Switching Mode Regula- low ESR ceramic capacitor.
tor Channel. The phase of CLKOUT with respect to CLKIN RUN1 (J8), RUN2 (L8): Run Control Input of Each 5A
is determined by the state of the respective PHMODE pin. Switching Mode Regulator Channel. Enable regulator
CLKOUT’s peak-to-peak amplitude is INTVCC to GND. See operation by tying the specific RUN pin above 1.2V. Tying
Applications Information section for details. it below 1.1V shuts down the specific regulator channel.
PHMODE0 (E6), PHMODE3 (R6): Control Input to the COMP1 (J11), COMP2 (M11): Current Control Threshold
Phase Selector of Each 12A Switching Mode Regulator and Error Amplifier Compensation Point of Each 5A Switch-
Channel. Determines the phase relationship between in- ing Mode Regulator Channel. The internal current compara-
ternal oscillator and CLKOUT. Tie it to INTVCC for 2-phase tor threshold is linearly proportional to this voltage. Tie the
operation, tie it to SGND for 3-phase operation, and float- COMP pins from different channels together for parallel
ing for 4-phase operation. See Applications Information operation. These channels are internally compensated.
section for details.

Rev. B

For more information www.analog.com 11

LTM4671
PIN FUNCTIONS
FB1 (H9), FB2 (M9): The Negative Input of the Error VOSNS1 (J10), VOSNS2 (L10): Output Voltage Sense Pin
Amplifier for Each 5A Switching Mode Regulator Channel. of Each 5A Switching Mode Regulator Channel. Internally,
This pin is internally connected to VOSNS1 or VOSNS2, this pin is connected to VFB with a 60.4k 0.5% precision
respectively, with a 60.4kΩ precision resistor. Output resistor. See the Applications Information section for
voltages can be programmed with an additional resistor details. It is very important to connect these pins to the
between FB and GND pins. In PolyPhase operation, tying VOUT since this is the feedback path, and cannot be left
the FB pins together allows for parallel operation. See the open. See the Applications Information section for details.
Applications Information section for details. MODE/CLKIN12 (L9): Mode Select and External Synchro-
TRACK/SS1 (G7), TRACK/SS2 (N7): Output Tracking nization Input Pin for Both 5A Switching Mode Regulator
and Soft-Start Pin of Each 5A Switching Mode Regulator Channels. Tie this pin to GND to force continuous synchro-
Channel. Allows the user to control the rise time of the nous operation. Floating this pin or tying it to INTVCC12
output voltage. Putting a voltage below 0.6V on this pin enables high efficiency Burst Mode operation at light
bypasses the internal reference input to the error amplifier, loads. When driving this pin with an external clock, the
instead it servos the FB pin to the TRACK voltage. Above phase-locked loop will force the channel 1 turn on signal
0.6V, the tracking function stops and the internal reference to be synchronized with the rising edge of the CLKIN12
resumes control of the error amplifier. There’s an internal signal. channel 2 will also be synchronized with the rising
1.4µA pull-up current from INTVCC on this pin, so putting edge of the CLKIN12 signal with a 180° phase shift. See
a capacitor here provides soft-start function. See the Ap- Applications Information section for details.
plications Information section for details. TMON (K8): Temperature Monitor for 5A Output Channels.
FREQ12 (K10): Switching Frequency Program Pin for Both A voltage proportional to the measured on-die temperature
5A Switching Mode Regulator Channels. Frequency is will appear at this pin. The voltage-to-temperature scaling
set internally to 1MHz. An external resistor can be placed factor is 200°K/V. See the Applications Information section
from this pin to GND to increase frequency, or from this for detailed information on the TMON function. Tie this pin
pin to INTVCC to reduce frequency. See the Applications to INTVCC12 to disable the temperature monitor circuit.
Information section for frequency adjustment.

Rev. B

12 For more information www.analog.com

 LTM4671
BLOCK DIAGRAM
MODE/CLKIN0 PGOOD0 100k
INTVCC0
VIN VIN
4V TO 20V
CLKOUT0 10µF
0.22µF
0.33µH VOUT1 VOUT0
INTVCC0 1.0V
2.2µF 12A
1µF 47µF
TRACK/SS0 GND
POWER CONTROL
0.1µF RUN0 VOSNS0–

COMP0a FB0 90.9k

15pF 60.4k VOSNS0+

COMP0b
PGOOD3 100k
INTERNAL COMP INTERNAL INTVCC3
FILTER
FREQ0 VIN
274k
0.22µF
MODE/CLKIN3
0.33µH VOUT3 VOUT3
INTVCC3 1.2V
12A
2.2µF 1µF 47µF
TRACK/SS3 POWER CONTROL GND

0.1µF RUN3 VOSNS3–

COMP3a 60.4k
FB3
15pF
COMP3b
60.4k VOSNS3+
INTERNAL COMP INTERNAL
FILTER
FREQ3 CLKOUT3

274k
VOSNS2

FB2 VOSNS1
13.3k
60.4k 60.4k PGOOD1 10k
FB1 INTVCC12

19.1k INTVCC12 PGOOD2 10k

INTVCC12
2.2µF
MODE/CLKIN12 VIN
0.22µF
TRACK/SS1
0.1µF 1µH VOUT1 VOUT1
2.5V
TRACK/SS2
5A
0.1µF RUN1 1µF 47µF
GND
RUN2 POWER CONTROL

COMP1

INTERNAL COMP
0.22µF
COMP2
1µH VOUT2 VOUT2
INTERNAL COMP 3.3V
5A
FREQ12 1µF 47µF
324k GND

Figure 1. Simplified LTM4671 Block Diagram

Rev. B

For more information www.analog.com 13

LTM4671
DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN External Input Capacitor Requirement 44 66 µF
(VIN = 3.1V to 20V, VOUT = 1.5V)
COUT0, COUT3 External Output Capacitor Requirement IOUT = 12A 100 200 µF
(VIN = 3.1V to 20V, VOUT = 1.5V)
COUT1, COUT2 External Output Capacitor Requirement IOUT = 5A 22 47 µF
(VIN = 3.1V to 20V, VOUT = 1.5V)

OPERATION
The LTM4671 is a quad output standalone non-isolated employ a 2+1+1 or 2+2 channels parallel operation which
switch mode DC/DC power supply. It has built-in four is more than flexible in a multirail POL application like
separate regulator channels which can deliver 12A, 12A, FPGA. Furthermore, the LTM4671 has CLKIN and CLKOUT
5A, 5A continuous output current with few external input pins for frequency synchronization or PolyPhase multiple
and output capacitors. Two 12A regulator provides pre- devices which allow up to 8 phases of 12A or 5A channels
cisely regulated output voltage programmable from 0.6V can be cascaded to run simultaneously.
to 3.3V via a single external resistor over 3.1V to 20V
input voltage range while the other two 5A regulator can Current mode control also provides cycle-by-cycle fast cur-
support output voltage from 0.6V to 5.5V. Dual true dif- rent monitoring. An internal overvoltage and undervoltage
ferential remote sensing amplifiers are included in the high comparators pull the open-drain PGOOD output low if the
current channels to get accurate regulation at load point. output feedback voltage exits a ±10% window around the
The typical application schematic is shown in Figure 30. regulation point. Furthermore, in an overvoltage condition,
internal top FET is turned off and bottom FET is turned on
The LTM4671 has integrated four separate constant on- and held on until the overvoltage condition clears.
time valley current mode regulators, power MOSFETs,
inductors, and other supporting discrete components. Pulling the RUN pin below 0.6V forces the controller into
For switching noise-sensitive applications, the switching its shutdown state, turning off both power MOSFETs and
frequency can be adjusted by external resistors and the most of the internal control circuitry. At light load currents,
µModule can be externally synchronized to a clock. See Burst Mode operation can be enabled to achieve higher
the Applications Information section. efficiency compared to continuous mode for the dual 5A
channels by setting MODE/PLLIN pin floating or tying
With current mode control and internal feedback loop to INTVCC. The TRACK/SS pin is used for power supply
compensation, the LTM4671 module has sufficient stabil- tracking and soft-start programming. See the Applications
ity margins and good transient performance with a wide Information section.
range of output capacitors, even with all ceramic output
capacitors. For Dual 12A output rails, an optional Type II Three different temperature sensing pins are included in-
C-R-C external compensation network is allowed to cus- side the module to monitor the temperature of the module
tomize the stability and transient performance. for different channels. See the Applications Information
section for details.
Current mode control provides the flexibility of paralleling
any of the separate regulator channels with accurate cur-
rent sharing. With a build in clock interleaving between
each two regulator channels, the LTM4671 could easily

Rev. B

14 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
The typical LTM4671 application circuit is shown in Figure For parallel operation of N-channels, tie the VOUT, the FB
30. External component selection is primarily determined pins and VOSNS– pins together but only hooking up one
by the input voltage, the output voltage and the maxi- VOSNS+ (VOSNS) pin to the VOUT so that all the parallel-
mum load current. Refer to Table 3 for specific external ing channels can share the same error amplifier and same
capacitor requirements for a particular application. top 60.4k feedback resistor. See PolyPhase Operation for
details.
VIN TO VOUT STEP-DOWN RATIOS
Table 1. VFB Resistor Table vs Various Output Voltages
There are restrictions in the maximum VIN and VOUT step- VOUT(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0
down ratio that can be achieved for a given input voltage RFB(k) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25
due to the minimum off-time and minimum on-time limits
of each regulator. The minimum off-time limit imposes a INPUT DECOUPLING CAPACITORS
maximum duty cycle which can be calculated as:
The LTM4671 module should be connected to a low AC-
D (MAX ) = 1– t OFF(MIN) • fSW impedance DC source. For each 12A regulator channel,
where tOFF(MIN) is the minimum off-time, 80ns typical for one piece 22µF input ceramic capacitor is required, for
LTM4671, and fSW is the switching frequency. Conversely, each 5A regulator channel, one piece 10µF input ceramic
the minimum on-time limit imposes a minimum duty cycle capacitor is required for RMS ripple current decoupling.
of the converter which can be calculated as: Bulk input capacitor is only needed when the input source
impedance is compromised by long inductive leads, traces
D (MIN) = t ON(MIN) • fSW
or not enough source capacitance. The bulk capacitor can be
an electrolytic aluminum capacitor and polymer capacitor.
where TON(MIN) is the minimum on-time, 25ns typical
for LTM4671. In the rare cases where the minimum duty Without considering the inductor current ripple, the RMS
cycle is surpassed, the output voltage will still remain in current of the input capacitor can be estimated as:
regulation, but the switching frequency will decrease from IOUT(MAX )
its programmed value. These constraints are shown in ICIN(RMS) = • D • (1– D)
η%
the Typical Performance Characteristic curve labeled “VIN
to VOUT Step-Down Ratio.” Note that additional thermal where η% is the estimated efficiency of the power module.
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet. OUTPUT DECOUPLING CAPACITORS

OUTPUT VOLTAGE PROGRAMMING With an optimized high frequency, high bandwidth design,
only single piece of low ESR output ceramic capacitor is
The PWM controller has an internal 0.6V reference voltage. required for each regulator channel to achieve low output
For the 12A channels (CH0, CH3), a 60.4k 0.5% internal voltage ripple and very good transient response. Additional
feedback resistor connects each regulator channel VOSNS+ output filtering may be required by the system designer,
and FB pin together. Adding a resistor RFB from FB pin to if further reduction of output ripples or dynamic transient
VOSNS– programs the output voltage. spikes is required. Table 3 shows a matrix of different output
voltages and output capacitors to minimize the voltage
For the 5A channels (CH1, CH2), a 60.4k 0.5% internal droop and overshoot during a 25% load step transient.
feedback resistor connects each regulator channel VOSNS Multiphase operation will reduce effective output ripple as
and FB pin together. Adding a resistor RFB from FB pin to a function of the number of phases. Application Note 77
GND programs the output voltage: discusses this noise reduction versus output ripple cur-
60.4k + R FB rent cancellation, but the output capacitance will be more
VOUT = 0.6V •
R FB
Rev. B

For more information www.analog.com 15

LTM4671
APPLICATIONS INFORMATION
a function of stability and transient response. The Analog reversal comparator (IREV) detects the negative inductor
Devices LTpowerCAD® Design Tool is available to download current and shuts off the bottom power MOSFET, resulting
online for output ripple, stability and transient response in discontinuous operation and increased efficiency. Both
analysis and calculating the output ripple reduction as power MOSFETs will remain off until the ITH voltage rises
the number of phases implemented increases by N times. above the zero current level to initiate another cycle. During
this time, the output capacitor supplies the load current
FORCED CONTINUOUS CURRENT MODE (CCM) and the part is placed into a low current sleep mode.
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest OPERATING FREQUENCY
output ripple is desired, forced continuous operation should The operating frequency of the LTM4671 is optimized
be used. In this mode, inductor current is allowed to reverse to achieve the compact package size and the minimum
during low output loads, the COMP voltage is in control output ripple voltage while still keeping high efficiency.
of the current comparator threshold throughout, and the The default operating frequency is internally set to 600kHz
top MOSFET always turns on with each oscillator pulse. for 12A channels and 1MHz for 5A channels. In most ap-
plications, no additional frequency adjusting is required.
For the 12A channels (CH0, CH3), CCM can be enabled
by tying the MODE/CLKIN0 or MODE/CLKIN3 pin to the For the 12A channels (CH0, CH3), if an operating frequency
respective INTVCC or simply floating it. other than 600kHz is required by the application, the op-
erating frequency can be increased by adding a resistor,
For the 5A channels (CH1, CH2), CCM can be enabled by
RFSET, between the FREQ0 or FREQ3 pins and SGND. The
tying the MODE/CLKIN12 pin to GND.
operating frequency can be calculated as:
During start-up, forced continuous mode is disabled and
inductor current is prevented from reversing until the 1.6e 11
f (Hz ) =
LTM4671’s output voltage is in regulation. 274k ||R FSET ( Ω )

The programmable operating frequency range is from

DISCONTINUOUS MODE/BURST MODE OPERATION
400kHz to 3MHz.
In applications where high efficiency at intermediate current
For the 5A channels (CH1, CH2), If an operating frequency
is desired, discontinuous mode or Burst Mode operation
other than 1MHz is required by the application, the op-
can be achieved.
erating frequency can be increased by adding a resistor,
For the 12A channels (CH0, CH3), discontinuous mode RFSET, between the FREQ12 pin and SGND. The operating
(DCM) can be achieved by tying the MODE/CLKIN0 or frequency can be calculated as:
MODE/CLKIN3 pin to GND. In discontinuous mode, the
reverse current comparator will sense the inductor current 3.2e 11
f (Hz ) =
and turn of bottom MOSFET when the inductor current 324k ||R FSET ( Ω )
drops to zero and becomes negative. Both power MOS-
FETs will remain off with the output capacitor supplying The programmable operating frequency range is from
the load current until the COMP voltage rises above its 400kHz to 3MHz.
zero current threshold to initiate the next switching cycle. Also the µModule can be externally synchronized to a clock
For the 5A channels (CH1, CH2), Burst Mode operation at ±30% around set operating frequency.
can be achieved by tying MODE/CLKIN12 pin to INTVCC12
or simply floating. In Burst Mode operation, a current

Rev. B

16 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
FREQUENCY SYNCHRONIZATION AND CLOCK IN
The power module has a phase-locked loop comprised MODE/CLKIN0 INTVCC0

of an internal voltage controlled oscillator and a phase VOUT0 CH0

(0°)
PHMODE0

detector. This allows all internal top MOSFET turn-on to CLKOUT0

be locked to the rising edge of the same external clock. 24A 180°
The external clock frequency range must be within ±30%
MODE/CLKIN3
around the set frequency. CH3
VOUT3 PHMODE3 FLOAT
(180°)
A pulse detection circuit is used to detect a clock on the CLKOUT3
MODE/CLKIN0 pin for CH0 (12A) channel, MODE/CLKIN3 90°
pin for CH3 (12A) channel and MODE/CLKIN12 pin for both
MODE/CLKIN12
CH1 and CH2 5A channels to turn on the phase-locked loop. CH1
VOUT1
(270°)
The pulse width of the clock has to be at least 400ns.
The clock high level must be above 1V and clock low 10A 180°
level below 0.3V. During the start-up of the regulator, the
phase-locked loop function is disabled. When the module
VOUT2 CH2
is driven with an external clock, forced continuous mode (90°)
(CCM) is automatically enabled.
LTM4671

MULTICHANNEL PARALLEL OPERATION

4671 F02

Figure 2. 2 + 2 Parallel Concept Schematic

For the application that demand more than 12A of output
current, the LTM4671 multiple regulator channels can be
pacitors. The RMS input ripple current is reduced by, and
easily paralleled to run out of phase to provide more output
the effective ripple frequency is multiplied by, the number
current without increasing input and output voltage ripples.
of phases used (assuming that the input voltage is greater
For the 12A channels (CH0, CH3), each channel has its than the number of phases used times the output voltage).
own MODE/CLKIN and CLKOUT pin. The CLKOUT signal The output ripple amplitude is also reduced by the number
can be connected to the CLKIN pin of the following stage to of phases used when all of the outputs are tied together
line up both frequency and the phase of the entire system. to achieve a single high output current design.
Tying the PHMODE pin to INTVCC, SGND or floating the pin
The LTM4671 device is an inherently current mode con-
generates a phase difference between the clock applied on
trolled device, so parallel modules will have very good
the MODE/CLKIN pin and CLKOUT of 180° degrees, 120°
current sharing. This will balance the thermals on the
degrees, or 90° degrees respectively, which corresponds
design. Please tie RUN, TRACK/SS, FB and COMP pins
to 2-phase, 3-phase, or 4-phase operation.
of each paralleling channel together. Figure 31 shows an
For the 5A channels (CH1, CH2), a preset built-in 180° example of parallel operation and pin connection.
phase different between channel 1 and channel 2. MODE/
CLKIN12 allows both channels to be synchronized to INPUT RMS RIPPLE CURRENT CANCELLATION
an external clock or the CLKOUT signal from any of the
12A channels. Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current
Figure 2 shows a 2 + 2 and a 4-channels parallel concept cancellation mathematical derivations are presented, and
schematic for clock phasing. a graph is displayed representing the RMS ripple current
A multiphase power supply significantly reduces the reduction as a function of the number of interleaved
amount of ripple current in both the input and output ca- phases. Figure 3 shows this graph.
Rev. B

For more information www.analog.com 17

LTM4671
APPLICATIONS INFORMATION
0.60
1-PHASE
2-PHASE
0.55 3-PHASE
4-PHASE
0.50 6-PHASE

0.45

0.40
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4671 F03

Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

SOFT-START AND OUTPUT VOLTAGE TRACKING Figure 4 and Figure 5 show an example waveform and
The TRACK/SS pin provides a means to either soft-start schematic of a ratiometric tracking where the slave
of each regulator channel or track it to a different power regulator’s (VOUT2, VOUT3 and VOUT0) output slew rate is
proportional to the master’s (VOUT1).
supply. A capacitor on the TRACK/SS pin will program the
ramp rate of the output voltage. An internal soft-start cur-
rent source will charge up the external soft-start capacitor
towards INTVCC voltage. When the TRACK/SS voltage is VOUT1 = 3.3V

below 0.6V, it will take over the internal 0.6V reference VOUT2 = 2.5V
voltage to control the output voltage. The total soft-start
OUTPUT VOLTAGE

time can be calculated as: VOUT3 = 1.2V

C SS VOUT0 = 1.0V
t SS = 0.6 •
ISS
where CSS is the capacitance on the TRACK/SS pin and
the ISS is the soft-start current which equals 6µA for the
12A output channels (CH0, CH3) and 1.4µA for the 5A TIME 4671 F04

Figure 4. Output Ratiometric Tracking Waveform

output channels (CH1, CH2).
Output voltage tracking can also be programmed externally
using the TRACK/SS pin of each regulator channel. The
output can be tracked up and down with another regulator.
Rev. B

18 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
VIN
4V TO 20V

VIN1

RUN1

VIN2

RUN2

VIN3
SVIN3
RUN3

VIN0
SVIN0
RUN0

LTM4671
CH1 CH2 CH3 CH0
TRACK/SS1

TRACK/SS2

TRACK/SS3

TRACK/SS0
VOUT1

VOUT2

VOUT3

VOUT0
FB1

FB2

FB3

FB0
4671 F05
3.3V/5A

CSS
RFB(SL)2 RFB(SL)3 RFB(SL)0
0.1µF
19.1k 60.4k 90.6k
2.5V/5A

1.2V/12A

1.0V/12A
RFB1
13.3k

RTR(TOP)2 RTR(BOT)2
60.4k 13.3k

RTR(TOP)3 RTR(BOT)3
60.4k 13.3k

RTR(TOP)0 RTR(BOT)0
60.4k 13.3k

Figure 5. Output Ratiometric Tracking Schematic

Since the slave regulator’s TRACK/SS is connected to For example, VOUT(MA) = 3.3V, MR = 3.3V/ms and VOUT(SL) =
the master’s output through a RTR(TOP)/RTR(BOT) resistor 1.0V, SR = 1.0V/ms as VOUT1 and VOUT0 from the equation,
divider and its voltage used to regulate the slave output we could solve out that RTR(TOP)0 = 60.4k and RTR(BOT)0 =
voltage when TRACK/SS voltage is below 0.6V, the slave 13.3k is a good combination. Follow the same equation,
output voltage and the master output voltage should satisfy we can get the same RTR(TOP)/RTR(BOT) resistor divider
the following equation during the start-up. value for VOUT2 and VOUT3.
R FB(SL ) R TR(BOT )
VOUT(SL ) • = VOUT(MA ) • The TRACK pins will have the 1.5µA current source on
R FB(SL ) + 60.4k R TR(TOP) + R TR(BOT ) when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
The RFB(SL) is the feedback resistor and the RTR(TOP)/ TRACK pin input. Smaller value resistors with the same
RTR(BOT) is the resistor divider on the TRACK/SS pin of ratios as the resistor values calculated from the above
the slave regulator, as shown in Figure 5. equation can be used. For example, where the 60.4k is
Following the upper equation, the master’s output slew used then a 6.04k can be used to reduce the TRACK pin
rate (MR) and the slave’s output slew rate (SR) in Volts/ offset to a negligible value.
Time is determined by: The coincident output tracking can be recognized as a
R FB(SL) special ratiometric output tracking which the master’s
MR R FB(SL) + 60.4k output slew rate (MR) is the same as the slave’s output
SR
=
R TR(BOT) slew rate (SR), see Figure 6.
R TR(TOP) + R TR(BOT)
Rev. B

For more information www.analog.com 19

LTM4671
APPLICATIONS INFORMATION
reduction, an additional 10pF to 15pF phase boost cap is
VOUT1 = 3.3V required between VOUT and FB pins.
VOUT2 = 2.5V For specific optimized requirement for the dual 12A chan-
nels, disconnect COMPb from COMPa and apply a Type II
OUTPUT VOLTAGE

VOUT3 = 1.2V
C-R-C compensation network from COMPa to SGND to
VOUT0 = 1.0V
achieve external compensation.
The LTpowerCAD design tool is available to download
online to perform specific control loop optimization and
analyze the control stability and load transient performance.
TIME 4671 F06

Figure 6. Output Coincident Tracking Waveform RUN ENABLE

Pulling the RUN pin of each regulator channel to ground
R FB(SL) R TR(BOT) forces the regulator into its shutdown state, turning off both
=
R FB(SL) + 60.4k R TR(TOP) + R TR(BOT) power MOSFETs and most of its internal control circuitry.
Bringing the RUN pin above 0.7V turns on the internal
From the equation, we could easily find out that, in the reference only, while still keeping the power MOSFETs
coincident tracking, the slave regulator’s TRACK/SS pin off. Further increasing the RUN pin voltage above 1.2V
resistor divider is always the same as its feedback divider. will turn on the entire regulator channel.
For example, RTR(TOP)3 = 60.4k and RTR(BOT)3 = 60.4k
is a good combination for coincident tracking for TEMPERATURE MONITORING
VOUT(MA) = 3.3V and VOUT(SL) =1.2V application.
The 12A Channels (CH0, CH3):
POWER GOOD Measuring the absolute temperature of a diode is pos-
sible due to the relationship between current, voltage
The PGOOD pins are open-drain pins that can be used to
and temperature described by the classic diode equation:
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. A resistor ⎛ V ⎞
can be pulled up to a particular supply voltage for moni- ID = IS • e ⎜ D ⎟
⎝ η • VT ⎠
toring. To prevent unwanted PGOOD glitches during tran-
sients or dynamic VOUT changes, the LTM4671’s PGOOD or
falling edge includes a blanking delay of approximately
52 switching cycles. I
VD = η • VT •In D
IS
STABILITY COMPENSATION
where ID is the diode current, VD is the diode voltage, η
The LTM4671 module internal compensation loop of each is the ideality factor (typically close to 1.0) and IS (satu-
regulator channel is designed and optimized for low ESR ration current) is a process dependent parameter. VT can
ceramic output capacitors only application (COMPb tied be broken out to:
to COMPa for 12A channels). Table 3 is provided for most
k•T
application requirements using the optimized internal VT =
compensation. In case of all ceramic output capacitors q
is required for output ripples or dynamic transient spike

Rev. B

20 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
where T is the diode junction temperature in Kelvin, q is 0.8

the electron charge and k is Boltzmann’s constant. VT is

approximately 26mV at room temperature (298K) and 0.7

scales linearly with Kelvin temperature. It is this linear

DIODE VOLTAGE (V)

temperature relationship that makes diodes suitable tem- 0.6

perature sensors. The IS term in the previous equation is

0.5
the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The IS term
0.4
varies from process to process, varies with temperature,
and by definition must always be less than ID. Combining 0.3
all of the constants into one term: –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) 4671 F07

η•k
KD = Figure 7. Diode Voltage VD vs Temperature T(°C)
q

where KD = 8.62−5, and knowing ln(ID/IS) is always posi- yields

tive because ID is always greater than IS, leaves us with
the equation that: ∆VD = K’D • T(KELVIN)
I Solving for temperature:
VD = T (KELVIN ) • K D •In D
IS ∆VD
T(KELVIN) = (°CELSIUS) = T(KELVIN) – 273.15
K'D
where VD appears to increase with temperature. It is com-
mon knowledge that a silicon diode biased with a current where
source has an approximate –2mV/°C temperature rela-
300°K = 27°C
tionship (Figure 7), which is at odds with the equation. In
fact, the IS term increases with temperature, reducing the means that is we take the difference in voltage across the
ln(ID/IS) absolute value yielding an approximate –2mV/°C diode measured at two currents with a ratio of 10, the
composite diode voltage slope. resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
To obtain a linear voltage proportional to temperature
we cancel the IS variable in the natural logarithm term to The diode connected NPN transistor across the TSENSEn+
remove the IS dependency from the equation 1. This is and pin and TSENSEn− pins can be used to monitor the
accomplished by measuring the diode voltage at two cur- internal temperature of the LTM4671 channel 0 and 3.
rents I1, and I2, where I1 = 10 • I2) and subtracting we get:
The 5A Channels (CH1, CH2):
I I
∆VD = T(KELVIN) • K D •IN 1 – T(KELVIN) • K D •IN 2 The LTM4671 produces a voltage at the TMON pin
IS IS proportional to the measured junction temperature. The
Combining like terms, then simplifying the natural log junction temperature-to-voltage scaling factor is 200°K/V.
terms yields: Thus, to obtain the junction temperature in degrees Kelvin,
simply multiply the voltage provided at the TMON pin by
∆VD = T(KELVIN) • KD • lN(10) the scaling factor. To obtain the junction temperature in
and redefining constant degrees Celsius, subtract 273 from the value obtained in
degrees Kelvin.
198µV
K'D = K D •IN(10) =
K
Rev. B

For more information www.analog.com 21

LTM4671
APPLICATIONS INFORMATION
2.0 1. θJA, the thermal resistance from junction to ambi-
1.9 ent, is the natural convection junction-to-ambient
1.8 air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
TMON VOLTAGE (V)

1.7

1.6 referred to as “still air” although natural convection

1.5 causes the air to move. This value is determined with
1.4 the part mounted to a JESD51-9 defined test board,
1.3 which does not reflect an actual application or viable
1.2 operating condition.
1.1
–50 –25 0 25 50 75 100 125 2. θJCbottom, the thermal resistance from junction to
TEMPERATURE (°C)
4671 F08
ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
Figure 8. TMON Voltage
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
Thermal Considerations and Output Current Derating causes the air to move. This value is determined with
The thermal resistances reported in the Pin Configuration the part mounted to a JESD51-9 defined test board,
section of the data sheet are consistent with those param- which does not reflect an actual application or viable
eters defined by JESD51-9 and are intended for use with operating condition.
finite element analysis (FEA) software modeling tools that 4. θJCtop, the thermal resistance from junction to top of
leverage the outcome of thermal modeling, simulation, and the product case, is determined with nearly all of the
correlation to hardware evaluation performed on a µModule component power dissipation flowing through the top
package mounted to a hardware test board—also defined of the package. As the electrical connections of the
by JESD51-9 (“Test Boards for Area Array Surface Mount typical µModule are on the bottom of the package, it
Package Thermal Measurements”). The motivation for is rare for an application to operate such that most of
providing these thermal coefficients in found in JESD51-12 the heat flows from the junction to the top of the part.
(“Guidelines for Reporting and Using Electronic Package As in the case of θJCbottom, this value may be useful
Thermal Information”). for comparing packages but the test conditions don’t
Many designers may opt to use laboratory equipment generally match the user’s application.
and a test vehicle such as the demo board to anticipate 5. θJB, the thermal resistance from junction to the
the µModule regulator’s thermal performance in their printed circuit board, is the junction-to-board thermal
application at various electrical and environmental operat- resistance where almost all of the heat flows through
ing conditions to compliment any FEA activities. Without the bottom of the µModule and into the board, and
FEA software, the thermal resistances reported in the is really the sum of the θJCbottom and the thermal re-
Pin Configuration section are in-and-of themselves not sistance of the bottom of the part through the solder
relevant to providing guidance of thermal performance; joints and through a portion of the board. The board
instead, the derating curves provided in the data sheet temperature is measured a specified distance from
can be used in a manner that yields insight and guidance the package, using a two sided, two layer board. This
pertaining to one’s application-usage, and can be adapted board is described in JESD51-9.
to correlate thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below.

Rev. B

22 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
A graphical representation of the aforementioned ther- resistance values supplied in this data sheet: (1) Initially,
mal resistances is given in Figure 9; blue resistances are FEA software is used to accurately build the mechanical
contained within the μModule regulator, whereas green geometry of the µModule and the specified PCB with all of
resistances are external to the µModule. the correct material coefficients along with accurate power
loss source definitions; (2) this model simulates a software-
As a practical matter, it should be clear to the reader that
defined JEDEC environment consistent with JSED 51-9 to
no individual or sub-group of the four thermal resistance
predict power loss heat flow and temperature readings
parameters defined by JESD51-12 or provided in the Pin
at different interfaces that enable the calculation of the
Configuration section replicates or conveys normal op-
JEDEC-defined thermal resistance values; (3) the model
erating conditions of a μModule. For example, in normal
and FEA software is used to evaluate the µModule with
board-mounted applications, never does 100% of the
heat sink and airflow; (4) having solved for and analyzed
device’s total power loss (heat) thermally conduct exclu-
these thermal resistance values and simulated various
sively through the top or exclusively through bottom of the
operating conditions in the software model, a thorough
µModule—as the standard defines for θJCtop and θJCbottom,
laboratory evaluation replicates the simulated conditions
respectively. In practice, power loss is thermally dissipated
with thermocouples within a controlled-environment
in both directions away from the package—granted, in the
chamber while operating the device at the same power
absence of a heat sink and airflow, a majority of the heat
loss as that which was simulated. An outcome of this
flow is into the board.
process and due-diligence yields a set of derating curves
Within a SIP (system-in-package) module, be aware there provided in other sections of this data sheet. After these
are multiple power devices and components dissipating laboratory tests have been performed and correlated to
power, with a consequence that the thermal resistances the µModule model, then the θJB and θBA are summed
relative to different junctions of components or die are not together to correlate quite well with the µModule model
exactly linear with respect to total package power loss. To with no airflow or heat sinking in a properly define chamber.
reconcile this complication without sacrificing modeling This θJB + θBA value is shown in the Pin Configuration
simplicity—but also, not ignoring practical realities—an section and should accurately equal the θJA value because
approach has been taken using FEA software modeling approximately 100% of power loss flows from the junc-
along with laboratory testing in a controlled-environment tion through the board into ambient with no airflow or top
chamber to reasonably define and correlate the thermal mounted heat sink.

JUNCTION-TO-AMBIENT RESISTANCE (JESD51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT

RESISTANCE RESISTANCE

JUNCTION-TO-BOARD RESISTANCE
JUNCTION AMBIENT

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE

4671 F09
µModule DEVICE

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. B

For more information www.analog.com 23

LTM4671
APPLICATIONS INFORMATION
The 1V to 5V power loss curves in Figure 10 to Figure junction temperature of 120°C minus the ambient operating
16 can be used in coordination with the load current temperature specifies how much module temperature rise
derating curves in Figure 17 to Figure 26 for calculating can be allowed. The printed circuit board for this test is a
an approximate θJA thermal resistance for the LTM4671 1.6mm thick six layers board with two ounce copper for
with various heat sinking and airflow conditions. The the two outer layers and one ounce copper for the four
power loss curves are taken at room temperature and inner layers. The PCB dimensions are 121mm × 112mm.
are increased with a multiplicative factor according to
Figure 27 and Figure 28 display the maximum power loss
the junction temperature. This approximate factor is 1.3
allowance curves vs ambient temperature with various
considering internal junction temperature hitting 120°C at
heat sinking and airflow conditions. This data was derived
the point of derating starts. The derating curves are taken
from the thermal derating curves in Figure 17 to Figure 26
with three different output power combinations, low power
with the junction temperature measured at 120°C. This
(VOUT0 = VOUT3 = 1V, VOUT1 = VOUT2 = 1.5V), medium
maximum power loss limitation serves as a guideline when
power (VOUT0 = VOUT3 = 1.8V, VOUT1 = VOUT2 = 3.3V) and
designing multiple output rails with different voltages and
high power (VOUT0 = VOUT3 = 3.3V, VOUT1 = VOUT2 = 5V).
currents by calculating the total power loss. For example,
Output current starting at 100% of the full load current
to determine the maximum ambient temperature when
(IOUT0 = IOUT3 = 12A, IOUT1 = IOUT2 = 5A) and the ambient
VIN = 12V, VOUT0 = 1V at 10A, VOUT1 = 1.8V at 3A, VOUT2
temperature starting at 30°C. These are chosen to include = 3.3V at 2A, VOUT3 = 1.5V at 10A, without a heat sink
the lower and higher output voltage ranges for correlating and any airflow, simply add up the total power loss for
the thermal resistance. Thermal models are derived from each channel read from Figure 10 to Figure 16 which in
several temperature measurements in a controlled tem- this example equals 4.8W (1.6W + 0.7W + 0.6W + 1.9W),
perature chamber along with thermal modeling analysis.
then multiply by the 1.3 coefficient for 120°C junction
The junction temperatures are monitored while ambient
temperature and compare the total power loss number,
temperature is increased with and without airflow. The
6.3W with Figure 27. Figure 27 indicates with a 6.3W total
power loss increase with ambient temperature change
power loss, the maximum ambient temperature for this
is factored into the derating curves. The junctions are
application is around 66°C. Also from Figure 27, it is easy
maintained at 120°C maximum while lowering output cur-
to determine with a 6.3W total power loss, the maximum
rent or power with increasing ambient temperature. The
ambient temperature is around 73°C with 200LFM airflow
decreased output current will decrease the internal module
and 77°C with 400LFM airflow.
loss as ambient temperature is increased. The monitored

Rev. B

24 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
3 3 3
2.8 5VIN, CH1, CH2 2.8 5VIN, CH1, CH2 2.8 5VIN, CH1, CH2
2.6 12VIN, CH1, CH2 2.6 12VIN, CH1, CH2 2.6 12VIN, CH1, CH2
2.4 5VIN, CH0, CH3 2.4 5VIN, CH0, CH3 2.4 5VIN, CH0, CH3
12VIN, CH0, CH3 12VIN, CH0, CH3 12VIN, CH0, CH3
2.2 2.2 2.2
POWER LOSS (W)

POWER LOSS (W)

POWER LOSS (W)

2 2 2
1.8 1.8 1.8
1.6 1.6 1.6
1.4 1.4 1.4
1.2 1.2 1.2
1 1 1
0.8 0.8 0.8
0.6 0.6 0.6
0.4 0.4 0.4
0.2 0.2 0.2
0 0 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12 0 2 4 6 8 10 12
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4671 F10 4671 F11 4671 F12

Figure 10. 1V Output Power Loss Figure 11. 1.2V Output Power Loss Figure 12. 1.5V Output Power Loss

3 4.0 4.0
2.8 5VIN, CH1, CH2 3.8 5VIN, CH1, CH2 3.8 5VIN, CH1, CH2
12VIN, CH1, CH2 3.6 12VIN, CH1, CH2 3.6 12VIN, CH1, CH2
2.6 3.4 3.4
5VIN, CH0, CH3 5VIN, CH0, CH3 5VIN, CH0, CH3
2.4 3.2 12VIN, CH0, CH3 3.2 12VIN, CH0, CH3
12VIN, CH0, CH3 3.0 3.0
2.2
2.8 2.8
POWER LOSS (W)

2
POWER LOSS (W)

POWER LOSS (W)

2.6 2.6
1.8 2.4 2.4
1.6 2.2 2.2
2.0 2.0
1.4 1.8 1.8
1.2 1.6 1.6
1 1.4 1.4
1.2 1.2
0.8 1.0 1.0
0.6 0.8 0.8
0.4 0.6 0.6
0.4 0.4
0.2 0.2 0.2
0 0 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12 0 2 4 6 8 10 12
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4671 F13 4671 F14 4671 F15

Figure 13. 5V Output Power Loss Figure 14. 2.5V Output Power Loss Figure 15. 3.3V Output Power Loss

4.0 120 120

3.8 12V , CH1, CH2
IN
3.6
3.4
LOAD CURRENT PERCENTAGE (%)

LOAD CURRENT PERCENTAGE (%)

100 100
3.2
3.0
2.8
80 80
POWER LOSS (W)

2.6
2.4
2.2
2.0 60 60
1.8
1.6
1.4 40 40
1.2
1.0
0.8
0.6 20 0LFM 20 0LFM
0.4 200LFM 200LFM
0.2 400LFM 400LFM
0 0 0
0 2 4 6 8 10 12 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F16 4671 F17 4671 F18

Figure 16. 5V Output Power Loss Figure 17. 5VIN Derating Curve, Figure 18. 5VIN Derating Curve,
No Heat Sink CH0 and CH3 with Heat Sink CH0 and CH3
Paralleled to 1V/24A CH1 and Paralleled to 1V/24A CH1 and CH2
CH2 Paralleled to 1.5V/10A Paralleled to 1.5V/10A
Rev. B

For more information www.analog.com 25

LTM4671
APPLICATIONS INFORMATION
120 120
LOAD CURRENT PERCENTAGE (%)

LOAD CURRENT PERCENTAGE (%)

100 100

80 80

60 60

40 40

20 0LFM 20 0LFM
200LFM 200LFM
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F19 4671 F20

Figure 19. 12VIN Derating Curve, No Heat Figure 20. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1V/24A Sink CH0 and CH3 Paralleled to 1V/24A
CH1 and CH2 Paralleled to 1.5V/10A CH1 and CH2 Paralleled to 1.5V/10A

120 120
LOAD CURRENT PERCENTAGE (%)

100 LOAD CURRENT PERCENTAGE (%) 100

80 80

60 60

40 40

20 0LFM 20 0LFM
200LFM 200LFM
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F21 4671 F22

Figure 21. 5VIN Derating Curve, No Heat Figure 22. 5VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A CH1 and CH2 Paralleled to 3.3V/10A

120 120
LOAD CURRENT PERCENTAGE (%)

LOAD CURRENT PERCENTAGE (%)

100 100

80 80

60 60

40 40

20 0LFM 20 0LFM
200LFM 200LFM
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F23 4671 F24

Figure 23. 12VIN Derating Curve, No Heat Figure 24. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A CH1 and CH2 Paralleled to 3.3V/10A
Rev. B

26 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
120 120
LOAD CURRENT PERCENTAGE (%)

LOAD CURRENT PERCENTAGE (%)

100 100

80 80

60 60

40 40

20 0LFM 20 0LFM
200LFM 200LFM
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F25 4671 F26

Figure 25. 12VIN Derating Curve, No Heat Figure 26. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 3.3V/24A Sink CH0 and CH3 Paralleled to 3.3V/24A
CH1 and CH2 Paralleled to 5V/10A CH1 and CH2 Paralleled to 5V/10A

12 12
11 11
10 10
9 9
8 8
POWER LOSS (W)
POWER LOSS (W)

7 7
6 6
5 5
4 4
3 3
2 0LFM 2 0LFM
200LFM 200LFM
1 1
400LFM 400LFM
0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4671 F27 4671 F28

Figure 27. Power Loss Allowance vs Figure 28. Power Loss Allowance vs
Ambient Temperature No Heat Sink Ambient Temperature with Heat Sink

Rev. B

For more information www.analog.com 27

LTM4671
APPLICATIONS INFORMATION
Table 2. Different Output, Junction-to-Ambient Thermal Resistance (θJA)
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figure 27 5, 12 Figure 10 to Figure 16 0 None 8.5
Figure 27 5, 12 Figure 10 to Figure 16 200 None 7
Figure 27 5, 12 Figure 10 to Figure 16 400 None 6.5
Figure 28 5, 12 Figure 10 to Figure 16 0 BGA Heat Sink 8
Figure 28 5, 12 Figure 10 to Figure 16 200 BGA Heat Sink 6
Figure 28 5, 12 Figure 10 to Figure 16 400 BGA Heat Sink 5.5

Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 30) 0A to 4A Load Step Typical Measured Values
CIN (CERAMIC) COUT (CERAMIC) COUT (BULK)
VENDORS VALUE PART NUMBER VENDORS VALUE PART NUMBER VENDORS VALUE PART NUMBER
Murata 22μF, 25V, X5R, 1206 GRT31CR61E226ME01L Murata 47μF, 6.3V, X5R, 0805 GRM21BR60J476ME15K Panasonic 680μF, 6.3V, 25mΩ 6TPE330ML
Murata 22μF, 25V, X5R, 1210 GRM32ER61E226KE15K Murata 100μF, 6.3V, X5R, 1210 GRM32ER60J107ME20L
Taiyo Yuden 22μF, 25V, X5R, 1206 TMK316BBJ226ML-T Taiyo Yuden 47μF, 6.3V, X5R, 0805 JMK212BBJ476MG-T
Taiyo Yuden 100μF, 6.3V, X5R, 1210 JMK325BJ107MM-T

CH0 and CH3 Transient Response

CIN COUT1 COUT2 P-P LOAD LOAD STEP
VOUT (CERAMIC) CIN* (CERAMIC) (BULK) CTH RTH CFF VIN DERIVATION RECOVERY STEP SLEW RATE RFB
(V) (μF) (BULK) (μF) (μF) (pF) (kΩ) (pF) (V) (mV) TIME (μs) (A) (A/μs) (k)
1 22 × 2 100 100 × 3 NA 1500 5 33 5, 12 79.7 30 3 10 90.9
1 22 × 2 100 100 330 1000 8 NA 5, 12 76.3 30 3 10 90.9
1.2 22 × 2 100 100 × 3 NA 1500 5 33 5, 12 83.7 30 3 10 60.4
1.2 22 × 2 100 100 330 1000 8 NA 5, 12 80 30 3 10 60.4
1.5 22 × 2 100 100 × 3 NA 1500 5 33 5, 12 90.4 30 3 10 40.2
1.5 22 × 2 100 100 330 1000 8 NA 5, 12 89.7 40 3 10 40.2
1.8 22 × 2 100 100 × 3 NA 1500 5 33 5, 12 103.8 30 3 10 30.1
1.8 22 × 2 100 100 330 1000 8 NA 5, 12 99.1 40 3 10 30.1
2.5 22 × 2 100 100 330 1000 8 NA 5, 12 147.3 50 3 10 19.1
3.3 22 × 2 100 100 330 1000 8 NA 5, 12 203 50 3 10 13.3
CH1 and CH2 Transient Response
CIN COUT1 COUT2 P-P LOAD LOAD STEP
VOUT (CERAMIC) CIN* (CERAMIC) (BULK) CTH RTH CFF VIN DERIVATION RECOVERY STEP SLEW RATE RFB
(V) (μF) (BULK) (μF) (μF) (pF) (kΩ) (pF) (V) (mV) TIME (μs) (A) (A/μs) (k)
1 22 100 47 × 2 NA Internal Internal 100 5, 12 56.9 50 1.25 10 90.9
1.2 22 100 47 × 2 NA Internal Internal 100 5, 12 57.8 60 1.25 10 60.4
1.5 22 100 47 × 2 NA Internal Internal 100 5, 12 62.3 60 1.25 10 40.2
1.8 22 100 47 × 2 NA Internal Internal 100 5, 12 67.6 70 1.25 10 30.1
2.5 22 100 47 × 2 NA Internal Internal 100 5, 12 85.7 70 1.25 10 19.1
3.3 22 100 47 × 2 NA Internal Internal 100 12 115 70 1.25 10 13.3
5 22 100 47 × 2 NA Internal Internal 100 12 167 70 1.25 10 8.25
*Optional

Rev. B

28 For more information www.analog.com

 LTM4671
APPLICATIONS INFORMATION
SAFETY CONSIDERATIONS • Place a dedicated power ground layer underneath
the unit.
The LTM4671 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required, • To minimize the via conduction loss and reduce module
a slow blow fuse with a rating twice the maximum input thermal stress, use multiple vias for interconnection
current needs to be provided to protect each unit from between top layer and other power layers.
catastrophic failure. The device does support thermal • Do not put via directly on the pad, unless they are
shutdown and over current protection. capped or plated over.
• Use a separated SGND ground copper area for com-
LAYOUT CHECKLIST/EXAMPLE
ponents connected to signal pins. Connect the SGND
The high integration of LTM4671 makes the PCB board to GND underneath the unit.
layout very simple and easy. However, to optimize its
• For parallel modules, tie the VOUT, VFB, and COMP pins
electrical and thermal performance, some layout con-
together. Use an internal layer to closely connect these
siderations are still necessary.
pins together. The TRACK pin can be tied a common
• Use large PCB copper areas for high current paths, capacitor for regulator soft-start.
including VIN, GND, VOUT1 and VOUT2. It helps to
• Bring out test points on the signal pins for monitoring.
minimize the PCB conduction loss and thermal stress.
Figure 29 gives a good example of the recommended layout.
• Place high frequency ceramic input and output
capacitors next to the VIN, PGND and VOUT pins to
minimize high frequency noise.

VOUT2 VOUT1 GND

GND

VOUT3 VOUT0

GND GND

GND

VIN
4671 F29

Figure 29. Recommended PCB Layout

Rev. B

For more information www.analog.com 29

LTM4671
TYPICAL APPLICATIONS

MODE/CLKIN0
CLKOUT0
MODE/CLKIN3
CLKOUT3
MODE/CLKIN12
INTVCC0
INTVCC3
INTVC12
VIN VIN1 VOUT0 VOUT0
5V TO 20V CIN VOSNS0+ COUT0 0.8V/12A
SVIN0 100µF ×4
22µF SVIN3 VOSNS0–
×4 182k
RUN0 FB0
RUN1
RUN2 VOUT1 VOUT1
RUN3 VOSNS1+ COUT1 1.8V/5A
30.1k
COMP0a FB1 47µF ×2
COMP0b
VOUT2 VOUT2
COMP1 VOSNS2+
LTM4671 COUT2 3.3V/5A
COMP2 13.3k
FB2 47µF ×2
COMP3a
COMP3b VOUT3 VOUT3
TRACK/SS0 VOSNS3+ COUT3 1.0V/12A
0.1μF TRACK/SS1 VOSNS3– 100µF ×4
TRACK/SS2 90.9k
0.1μF FB3
0.1μF TRACK/SS3
0.1μF PGOOD0
PGOOD1
PHMODE3
PHMODE0

PGOOD2
FREQ12
FREQ3
FREQ0

TMON
PGOOD3

GND
4671 F30

Figure 30. 5V to 20V Input, Quad Output Design

Rev. B

30 For more information www.analog.com

 LTM4671
TYPICAL APPLICATIONS
INTVCC0

MODE/CLKIN0
CLKOUT0
MODE/CLKIN3
CLKOUT3
MODE/CLKIN12
INTVCC0
INTVCC3
INTVC12
VIN VIN1 VOUT0 VOUT0
5V TO 20V CIN SVIN0 VOUT3 1.0V/24A
22µF SVIN3 COUT0
×4 VOSNS0+
RUN0 100µF ×6
VOSNS3+
RUN1
RUN2
VOSNS0–
RUN3
VOSNS3–
COMP0a
COMP0b 90.0k
FB0
COMP1 FB3
COMP2 LTM4671
VOUT1 VOUT1
COMP3a VOUT2 3.3V/10A
COMP3b
COUT1
TRACK/SS0 VOSNS1+ 47µF ×4
0.1μF TRACK/SS1 VOSNS2+
0.1μF TRACK/SS2
0.1μF TRACK/SS3 FB1 13.3k
0.1μF FB2
PGOOD0
PGOOD1
PHMODE0
PHMODE3

PGOOD2
FREQ12
FREQ3
FREQ0

TMON
PGOOD3

GND
4671 F31

400k 400k

INTVCC0

CH0 CH1 CH2 CH3

Phase Shift 180° 90° 180°
Phase 0° 180° 270° 90°

Figure 31. Parallel Operation with 1MHz Clock and Interleaved Phases

Rev. B

For more information www.analog.com 31

LTM4671
TYPICAL APPLICATIONS

MODE/CLKIN0
CLKOUT0
MODE/CLKIN3
CLKOUT3
MODE/CLKIN12
INTVCC0
INTVCC3
INTVC12
VIN VIN1 VOUT0 VOUT0
3.3V CIN VOSNS0+ COUT0 0.8V/12A
SVIN0 100µF ×4
22µF SVIN3 VOSNS0–
×4 182k
RUN0 FB0 VOUT1
RUN1 1.8V/5A
RUN2 VOUT1
RUN3 VOSNS1+ COUT1
30.1k
COMP0a FB1 47µF ×2
COMP0b
LTM4671 VOUT2 VOUT2
COMP1 VOSNS2+
COUT2 1.2V/5A
COMP2 60.4k
FB2 47µF ×2
COMP3a
COMP3b VOUT3 VOUT3
PGOOD0 VOSNS3+ COUT3 1.0V/12A
PGOOD1 VOSNS3– 100µF ×4
PGOOD2 90.9k 60.4k
FB3
PGOOD3
TRACK/SS0
TRACK/SS1
0.1µF 60.4k 60.4k
PHMODE3
PHMODE0
FREQ12
FREQ3
FREQ0

TMON

TRACK/SS2
GND

TRACK/SS3
4671 F32
30.1k 30.1k 30.1k

Figure 32. 3.3VIN , 1.8V, 1.2V, 1V, 0.8V with Ratiometric Tracking

Rev. B

32 For more information www.analog.com

 LTM4671
COMPONENT BGA PINOUT
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VOUT0 B1 VOUT0 C1 VOUT0 D1 VOUT0 E1 VOUT0
A2 VOUT0 B2 VOUT0 C2 VOUT0 D2 VOUT0 E2 VOUT0
A3 VOUT0 B3 VOUT0 C3 VOUT0 D3 VOUT0 E3 GND
A4 GND B4 GND C4 GND D4 GND E4 GND
A5 GND B5 GND C5 GND D5 GND E5 GND
A6 TSENSE0– B6 GND C6 GND D6 GND E6 PHMODE0
A7 TSENSE0+ B7 GND C7 GND D7 VIN E7 INTVCC0
A8 GND B8 GND C8 GND D8 VIN E8 VIN
A9 GND B9 GND C9 GND D9 VIN E9 SVIN0
A10 GND B10 GND C10 GND D10 VIN E10 CLKOUT0
A11 GND B11 GND C11 GND D11 VIN E11 PGOOD0

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
F1 GND G1 GND H1 VOUT1 J1 VOUT1 K1 GND
F2 GND G2 GND H2 VOUT1 J2 VOUT1 K2 GND
F3 GND G3 GND H3 VOUT1 J3 VOUT1 K3 GND
F4 GND G4 GND H4 VOUT1 J4 VOUT1 K4 GND
F5 GND G5 GND H5 GND J5 VIN K5 GND
F6 GND G6 GND H6 VIN J6 VIN K6 GND
F7 GND G7 TRACK/SS1 H7 GND J7 GND K7 GND
F8 VOSNS0– G8 V0SNS0+ H8 PGOOD1 J8 RUN1 K8 TMON
F9 TRACK/SS0 G9 FB0 H9 FB1 J9 GND K9 INTVCC12
F10 FREQ0 G10 GND H10 COMP0a J10 VOSNS1+ K10 FREQ12
F11 RUN0 G11 MODE/CLKIN0 H11 COMP0b J11 COMP1 K11 GND

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
L1 VOUT2 M1 VOUT2 N1 GND P1 GND R1 VOUT3
L2 VOUT2 M2 VOUT2 N2 GND P2 GND R2 VOUT3
L3 VOUT2 M3 VOUT2 N3 GND P3 GND R3 GND
L4 VOUT2 M4 VOUT2 N4 GND P4 GND R4 GND
L5 VIN M5 GND N5 GND P5 GND R5 GND
L6 VIN M6 VIN N6 GND P6 CLKOUT3 R6 PHMODE3
L7 GND M7 GND N7 TRACK/SS2 P7 RUN3 R7 PGOOD3
L8 RUN2 M8 PGOOD2 N8 COMP3b P8 FREQ3 R8 MODE/CLKIN3
L9 MODE/CLKIN12 M9 FB2 N9 COMP3a P9 TRACK/SS3 R9 SVIN3
L10 V0SNS2+ M10 GND N10 FB3 P10 V0SNS3– R10 VIN
L11 GND M11 COMP2 N11 V0SNS3+ P11 GND R11 INTVCC3

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

T1 VOUT3 U1 VOUT3 V1 VOUT3 W1 VOUT3
T2 VOUT3 U2 VOUT3 V2 VOUT3 W2 VOUT3
T3 VOUT3 U3 VOUT3 V3 VOUT3 W3 VOUT3
T4 GND U4 GND V4 GND W4 GND
T5 GND U5 GND V5 GND W5 GND
T6 GND U6 GND V6 GND W6 TSENSE3+
T7 VIN U7 GND V7 GND W7 TSENSE3–
T8 VIN U8 GND V8 GND W8 GND
T9 VIN U9 GND V9 GND W9 GND
T10 VIN U10 GND V10 GND W10 GND
T11 VIN U11 GND V11 GND W11 GND
Rev. B

For more information www.analog.com 33

LTM4671
PACKAGE DESCRIPTION

BGA Package
209-Lead (16mm × 9.50mm × 4.72mm)
(Reference LTC DWG# 05-08-1561 Rev B)
SEE NOTES
A DETAIL A
2× aaa Z 7
E Y
X A2 SEE NOTES 11 10 9 8 7 6 5 4 3 2 1
3 PIN 1

Z
A
A1

PIN “A1” B
ccc Z
CORNER
C
4
b D

E
b1
MOLD
F
CAP
SUBSTRATE G
H1
H2 H

J
// bbb Z

D
DETAIL B F K

M
Øb (209 PLACES) e
N
ddd M Z X Y
eee M Z P

V
DETAIL A W
2× aaa Z
e b
PACKAGE TOP VIEW G

DETAIL B
PACKAGE BOTTOM VIEW
PACKAGE SIDE VIEW
4.00

3.20

2.40

1.60

0.80

0.00

0.80

1.60

2.40

3.20

4.00

7.20 NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
0.40 ±0.025 Ø 209x 6.40 DIMENSIONS
2. ALL DIMENSIONS ARE IN MILLIMETERS
5.60 SYMBOL MIN NOM MAX NOTES
A 4.53 4.72 4.91 3 BALL DESIGNATION PER JEP95
4.80
A1 0.30 0.40 0.50 BALL HT 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
4.00 BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
A2 4.23 4.32 4.41
3.20 b 0.45 0.50 0.55 BALL DIMENSION THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
2.40 b1 0.37 0.40 0.43 PAD DIMENSION
D 16.00 5. PRIMARY DATUM -Z- IS SEATING PLANE
1.60
E 9.50 6 PACKAGE ROW AND COLUMN LABELING MAY VARY
0.80
e 0.80 ! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
0.00 F 14.40
0.80 G 8.00
H1 0.32 SUBSTRATE THK
1.60
H2 4.00 MOLD CAP HT
2.40
aaa 0.15
3.20 bbb 0.20
4.00 ccc 0.20
ddd 0.15 LTMXXXX
4.80 COMPONENT µModule
eee 0.08 PIN “A1”
5.60 TOTAL NUMBER OF BALLS: 209
6.40
TRAY PIN 1
7.20 BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
BGA 209 0218 REV B
SUGGESTED PCB LAYOUT
TOP VIEW

Rev. B

34 For more information www.analog.com

 LTM4671
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/19 Corrected value of Start-Up Waveform graphs from 2ms/DIV to 20ms/DIV 8
B 01/20 Added text and formula to set operating frequency 16
Added Temperature Monitering section 20, 21, 22
Changed MAX Value of Line Regulation Accuracy to 0.05% 3, 4

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 35
LTM4671
PACKAGE PHOTO

DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design: Manufacturing:
• Selector Guides • Quick Start Guide
• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools • Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.

Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.

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Rev. B

36
01/20
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