74AC00 • 74ACT00 Quad 2-Input NAND Gate
November 1988
Revised February 2005
74AC00 • 74ACT00
Quad 2-Input NAND Gate
General Description Features
The AC/ACT00 contains four 2-input NAND gates. ■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT00 has TTL-compatible inputs
Ordering Code:
Package
Order Number Package Description
Number
74AC00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC00SCX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74AC00PC_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT00SCX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. PC not available in Tape and Reel.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.
Logic Symbol Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names Description
An, Bn Inputs
On Outputs
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation DS009911 www.fairchildsemi.com
74AC00 • 74ACT00
Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC) 0.5V to 7.0V Conditions
DC Input Diode Current (IIK) Supply Voltage (VCC)
VI 0.5V 20 mA AC 2.0V to 6.0V
VI VCC 0.5V 20 mA ACT 4.5V to 5.5V
DC Input Voltage (VI) 0.5V to VCC 0.5V Input Voltage (VI) 0V to VCC
DC Output Diode Current (IOK) Output Voltage (VO) 0V to VCC
VO 0.5V 20 mA Operating Temperature (TA) 40qC to 85qC
VO VCC 0.5V 20 mA Minimum Input Edge Rate ('V/'t)
DC Output Voltage (VO) 0.5V to VCC 0.5V AC Devices
DC Output Source VIN from 30% to 70% of VCC
or Sink Current (IO) r50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
DC VCC or Ground Current Minimum Input Edge Rate ('V/'t)
per Output Pin (ICC or IGND) r50 mA ACT Devices
Storage Temperature (TSTG) 65qC to 150qC VIN from 0.8V to 2.0V
Junction Temperature (TJ) VCC @ 4.5V, 5.5V 125 mV/ns
PDIP 140qC Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT 50 PA
5.5 5.49 5.4 5.4
VIN VIL or VIH
3.0 2.56 2.46 IOH 12 mA
4.5 3.86 3.76 V IOH 24 mA
5.5 4.86 4.76 IOH 24 mA (Note 3)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT 50 PA
5.5 0.001 0.1 0.1
VIN VIL or VIH
3.0 0.36 0.44 IOL 12 mA
4.5 0.36 0.44 V IOL 24 mA
5.5 0.36 0.44 IOL 24 mA (Note 3)
IIN Maximum Input 5.5 r0.1 r1.0 PA VI VCC, GND
(Note 4) Leakage Current
IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Max
IOHD Output Current (Note 5) 5.5 75 mA VOHD 3.85V Min
ICC Maximum Quiescent Supply Current 5.5 2.0 20.0 PA VIN VCC or GND
(Note 4)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
www.fairchildsemi.com 2
74AC00 • 74ACT00
DC Electrical Characteristics for ACT
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VOUT 0.1V
V
Input Voltage 5.5 1.5 2.0 2.0 or VCC 0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VOUT 0.1V
V
Input Voltage 5.5 1.5 0.8 0.8 or VCC 0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4
V IOUT 50 PA
Output Voltage 5.5 5.49 5.4 5.4
VIN VIL or VIH
4.5 3.86 3.76 IOH 24 mA
V
5.5 4.86 4.76 IOH 24 mA (Note 6)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1
V IOUT 50 PA
Output Voltage 5.5 0.001 0.1 0.1
VIN VIL or VIH
4.5 0.36 0.44 V IOL 24 mA
5.5 0.36 0.44 IOL 24 mA (Note 6)
IIN Maximum Input 5.5 r0.1 r1.0 PA VI VCC, GND
Leakage Current
ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI VCC 2.1V
IOLD Minimum Dynamic 5.5 75 mA VOLD 1.65V Max
IOHD Output Current (Note 7) 5.5 75 mA VOHD 3.85V Min
ICC Maximum Quiescent 5.5 2.0 20.0 PA VIN VCC
Supply Current or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 8) Min Typ Max Min Max
tPLH Propagation Delay 3.3 2.0 7.0 9.5 2.0 10.0
ns
5.0 1.5 6.0 8.0 1.5 8.5
tPHL Propagation Delay 3.3 1.5 5.5 8.0 1.0 8.5
ns
5.0 1.5 4.5 6.5 1.0 7.0
Note 8: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
AC Electrical Characteristics for ACT
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) CL 50 pF CL 50 pF Units
(Note 9) Min Typ Max Min Max
tPLH Propagation Delay 5.0 1.5 5.5 9.0 1.0 9.5 ns
tPHL Propagation Delay 5.0 1.5 4.0 7.0 1.0 8.0 ns
Note 9: Voltage Range 5.0 is 5.0V r0.5V
Capacitance
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC Open
CPD Power Dissipation Capacitance 30.0 pF VCC 5.0V
3 www.fairchildsemi.com
74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com 4
74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5 www.fairchildsemi.com
74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com 6
74AC00 • 74ACT00 Quad 2-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
7 www.fairchildsemi.com
