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Issues: verilog-to-routing/vtr-verilog-to-routing

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Issues list

Use channel widths calculated from the rr-graph for drawing and linear congestion
#3100 opened Jun 2, 2025 by soheilshahrouz
@soheilshahrouz
Improve NoC arch tag documentation, and add ability to use equations in NoC tags
#2948 opened Mar 21, 2025 by vaughnbetz
@soheilshahrouz
Change default noc_biased_centroid_move weight
#2936 opened Mar 17, 2025 by vaughnbetz
@soheilshahrouz
Document Hermes benchmark suite
#2908 opened Feb 24, 2025 by vaughnbetz
@soheilshahrouz
Comparing performance/quality trade-off of SPEC and VTR random number generators.
#2798 opened Nov 3, 2024 by soheilshahrouz
@soheilshahrouz
Make a short coding style guide in the VTR developer guide
#2678 opened Aug 6, 2024 by vaughnbetz
@soheilshahrouz
Remove +1 from wirelength estimate
#2655 opened Jul 18, 2024 by amin1377
@vaughnbetz @amin1377 @soheilshahrouz
1
Detailed NoC Usage (Latency Etc.) Report
#2464 opened Dec 4, 2023 by vaughnbetz
@soheilshahrouz
2
Clock routing enhancements no-stale Exclude issue from being automatically marked as stale VPR VPR FPGA Placement & Routing Tool
#971 opened Sep 19, 2019 by vaughnbetz
@soheilshahrouz
6
ProTip! What’s not been updated in a month: updated:<2025-05-12.