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Issues: verilog-to-routing/vtr-verilog-to-routing

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Issues list

Support for simple dual port RAMs in ODIN/ODIN+Yosys Odin Odin II Logic Synthesis Tool: Unsorted item Yosys+Odin-II The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow
#2123 opened Aug 11, 2022 by aman26kbm
@KennethKent @loglav03
4
Improve VPR Regression Test Coverage Good First Issue Good issues for new or first-time contributors tests VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#531 opened Apr 8, 2019 by kmurray
@vaughnbetz
4
Benchmarking Enhancements no-stale Exclude issue from being automatically marked as stale
#546 opened Apr 26, 2019 by rfungquicklogic
@vaughnbetz @AmirhosseinPoolad
3
Regression Tests should check average/geomean QoR metrics no-stale Exclude issue from being automatically marked as stale tests VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#630 opened May 31, 2019 by kmurray
@renrichard @AmirhosseinPoolad
6
Clock routing enhancements no-stale Exclude issue from being automatically marked as stale VPR VPR FPGA Placement & Routing Tool
#971 opened Sep 19, 2019 by vaughnbetz
@soheilshahrouz
6
Create VPR timing report on unconstrained paths tatum Tatum timing analyzer
#1022 opened Oct 30, 2019 by vaughnbetz
@AlexandreSinger
4
Differentiate clock from other routing (better filtering in graphics) Good First Issue Good issues for new or first-time contributors VPR VPR FPGA Placement & Routing Tool
#1616 opened Dec 17, 2020 by vaughnbetz
@SamuelHo10
5
Update vtr_vector_map comment to recommend vtr_vector
#1650 opened Jan 28, 2021 by vaughnbetz
@sfkhalid
3
Remove excessive / spurious rr-graph warnings about inability to make direct connections at the edge of the chip
#1702 opened Apr 1, 2021 by vaughnbetz
@SamuelHo10
3
Make run_vtr_task/run_vtr_flow/config.txt all support directories with multiple files per benchmark
#1774 opened Jun 10, 2021 by vaughnbetz
@jgoeders @AlexandreSinger
3
Remove some out of date TO-DO and comments in rr_graph.cpp
#1995 opened Mar 10, 2022 by vaughnbetz
@tangxifan @behzadmehmood-rs
5
Needed features in VTR description to represent Xilinx architecture
#2071 opened Jun 23, 2022 by WhiteNinjaZ
7 of 12 tasks
1
Add check to router that estimated delay in wave expansion is the same as the traceback delay achieved enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool
#382 opened Aug 9, 2018 by vaughnbetz
@vaughnbetz
2
VPR Pack: Replace hand-implemented linked lists to std::lists
#2088 opened Jul 7, 2022 by jmah76
@AmirhosseinPoolad
4
Improve / suppress / control overly picky and frequent RR-graph warnings no-stale Exclude issue from being automatically marked as stale
#2199 opened Nov 11, 2022 by vaughnbetz
@AmirhosseinPoolad
3
Unexpected attribute 'tileable' found on node 'layout'
#2247 opened Feb 22, 2023 by zliu1Charlotte
3
Wrong blif for subtractor for different architecture files
#2266 opened Mar 30, 2023 by FPGA1234
@alirezazd @loglav03
5
vpr graphics only show final results (post-routing)
#2320 opened May 23, 2023 by vaughnbetz
@SamuelHo10
3
Docker image doesn't support vpr graphics
#2321 opened May 24, 2023 by vaughnbetz
@SamuelHo10
3
Allow pin offsets (x, y, layer) in connection block specifications to build the rr-graph
#2322 opened May 24, 2023 by vaughnbetz
@saaramahmoudi @amin1377
2
VPR creates error when class="memory" is used with a single-port BRAM
#2362 opened Aug 8, 2023 by AhmadHouraniah
1
How to run the Koios benchmarks for QoR
#2401 opened Sep 25, 2023 by vaughnbetz
@saaramahmoudi @aman26kbm @AlexandreSinger
7
Flat router delays in timing report are inaccurate due to treating clock as global net
#2413 opened Oct 6, 2023 by saaramahmoudi
@amin1377
4
Detailed NoC Usage (Latency Etc.) Report
#2464 opened Dec 4, 2023 by vaughnbetz
@soheilshahrouz
3
Portable VTR Release with a Static Build of VTR
#3122 opened Jun 8, 2025 by stefanpie
1
ProTip! What’s not been updated in a month: updated:<2025-05-15.