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Issues: verilog-to-routing/vtr-verilog-to-routing

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Issues list

VTR throws warning for shorted SB connections
#2712 by WhiteNinjaZ was closed Jan 18, 2025
@WhiteNinjaZ
Designs with many different wire types fail at certain channel widths with an arithmetic exception
#2497 by WhiteNinjaZ was closed Jan 10, 2025
@WhiteNinjaZ
run_vtr_flow currently does not properly handle sdc files Stale
#2420 by WhiteNinjaZ was closed May 27, 2025
@WhiteNinjaZ
1
Segment Usage by Type does not return the values that the title would suggest it should
#2399 by WhiteNinjaZ was closed Oct 6, 2023
@amin1377
1
Current Switch Override Implementation Strategy Doesn't Make Much Electrical Sense
#2195 by WhiteNinjaZ was closed Jan 10, 2025
1
Dangling interconnect occurs when connecting a wire to a switch of type short
#2064 by WhiteNinjaZ was closed May 18, 2023
@SebastianLievano
7
Unable to Describe Diagonal Wires with Current VPR architecture description
#2043 by WhiteNinjaZ was closed Sep 1, 2022
1
4
Segment SB pattern does not allow for zero fan out on ends Stale
#2039 by WhiteNinjaZ was closed Jun 2, 2025
2
Update documentation to reflect recent changes in specifying different x and y segment lengths
#2023 by WhiteNinjaZ was closed May 19, 2022
1
@WhiteNinjaZ
Allow for graphical representation of an architecture without having to build and implement a design Stale
#2016 by WhiteNinjaZ was closed Jun 2, 2025
2
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