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Issues: verilog-to-routing/vtr-verilog-to-routing
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VTR seems to struggle with being smart about how it packs into memories
#2718
opened Sep 12, 2024 by
WhiteNinjaZ
Parmys fails to properly handle multipliers with unequal input widths
#2532
opened Apr 11, 2024 by
WhiteNinjaZ
Needed features in VTR description to represent Xilinx architecture
#2071
opened Jun 23, 2022 by
WhiteNinjaZ
7 of 12 tasks
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