-
Notifications
You must be signed in to change notification settings - Fork 417
Issues: verilog-to-routing/vtr-verilog-to-routing
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
using `define with binary operation in range causes segmentation fault
#231
by jeanlego
was closed Aug 20, 2017
soft-logic adders circuit type request
enhancement
Feature enhancement
help wanted
Odin
Odin II Logic Synthesis Tool: Unsorted item
#275
by jeanlego
was closed Jan 15, 2018
ODIN mapping to constants directly in the module instantiation crashes when used as array ref inside the module
bug
Incorrect behaviour
Good First Issue
Good issues for new or first-time contributors
Odin
Odin II Logic Synthesis Tool: Unsorted item
#361
by jeanlego
was closed Jun 12, 2018
Broken tables in the docs
bug
Incorrect behaviour
docs
Documentation
help wanted
#389
by mithro
was closed Apr 12, 2019
Improve Router Costing of Non-configurably Connected Nodes
enhancement
Feature enhancement
VPR
VPR FPGA Placement & Routing Tool
#525
by kmurray
was closed May 21, 2019
I looking for help to compile synth as an exe file on windows.
#561
by Abdurrahman-Knifati
was closed May 11, 2019
ODIN: support for tri0 tri1 primitive and for inlining within module declaration
#605
by jeanlego
was closed Feb 15, 2020
Power estimation could not be implemented for certain circuits
#1323
by Niranjananiranju
was closed Jun 1, 2020
Previous Next
ProTip!
Type g p on any issue or pull request to go back to the pull request listing page.