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Issues: verilog-to-routing/vtr-verilog-to-routing
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VPR creates error when class="memory" is used with a single-port BRAM
#2362
opened Aug 8, 2023 by
AhmadHouraniah
Change RRG storage to keep (drive pt, direction) instead of (start, end)
Stale
#2491
opened Feb 20, 2024 by
duck2
Missing documentaion for some 3D-related tags and fields in the architecture reference
#2628
opened Jun 24, 2024 by
soheilshahrouz
Relax when router lookahead issues warnings for failure to find sample locations
#2636
opened Jun 30, 2024 by
petergrossmann21
Needed features in VTR description to represent Xilinx architecture
#2071
opened Jun 23, 2022 by
WhiteNinjaZ
7 of 12 tasks
VTR seems to struggle with being smart about how it packs into memories
#2718
opened Sep 12, 2024 by
WhiteNinjaZ
Improve 3D switch block commenting and move command line option to arch file
#2722
opened Sep 13, 2024 by
vaughnbetz
3 tasks
Packing Devices from Two Separate Parts of a Netlist into a Single CLB
#2726
opened Sep 17, 2024 by
WindFrank
[Packer] Setting Higher Target Pin Utilization When Regions are Full
VPR
VPR FPGA Placement & Routing Tool
#2729
opened Sep 20, 2024 by
AlexandreSinger
[ClusterLegalizer] Code Cleanups
VPR
VPR FPGA Placement & Routing Tool
#2730
opened Sep 20, 2024 by
AlexandreSinger
4 of 6 tasks
[Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer
VPR
VPR FPGA Placement & Routing Tool
#2731
opened Sep 20, 2024 by
AlexandreSinger
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