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Issues: verilog-to-routing/vtr-verilog-to-routing
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[STA] Post-Implementation STA Support for Dedicated Clock Network Modeling
#3027
opened May 7, 2025 by
AlexandreSinger
Use of Equivalent Sites Ambiguates PB Type Usage in Place and Route
#2888
opened Feb 7, 2025 by
petergrossmann21
Relax when router lookahead issues warnings for failure to find sample locations
#2636
opened Jun 30, 2024 by
petergrossmann21
Wire lookahead runtime scales poorly with number of switch/segment types
#2811
opened Nov 15, 2024 by
petergrossmann21
Change RRG storage to keep (drive pt, direction) instead of (start, end)
Stale
#2491
opened Feb 20, 2024 by
duck2
[Packer] Prepacker handling of pack pattern pins with net fanout > 1
#2996
opened Apr 22, 2025 by
amin1377
[Pack][Timing] Pre-Cluster Timing Analysis May Not Be Aware of Molecules
#2972
opened Apr 11, 2025 by
AlexandreSinger
Packing Devices from Two Separate Parts of a Netlist into a Single CLB
#2726
opened Sep 17, 2024 by
WindFrank
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