Skip to content

Issues: verilog-to-routing/vtr-verilog-to-routing

Beta
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
56 Open 596 Closed
56 Open 596 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Constant and inverter "replication" during packing
#2606 opened Jun 11, 2024 by rs-dhow updated Jun 19, 2024
2
Missing documentaion for some 3D-related tags and fields in the architecture reference
#2628 opened Jun 24, 2024 by soheilshahrouz updated Jun 24, 2024
Upgrade Self-Hosted Runners to Node20
#2573 opened May 31, 2024 by AlexandreSinger updated Jul 5, 2024
8
Placement Internals Document
#2650 opened Jul 17, 2024 by amin1377 updated Jul 17, 2024
Placement channel_width_fac
#2651 opened Jul 17, 2024 by amin1377 updated Jul 18, 2024
Fc_override Not Parsed Correctly
#2658 opened Jul 22, 2024 by WhiteNinjaZ updated Jul 22, 2024
1
[CI] Investigating CI Runners
#2652 opened Jul 18, 2024 by AlexandreSinger updated Jul 23, 2024
5
Relax when router lookahead issues warnings for failure to find sample locations
#2636 opened Jun 30, 2024 by petergrossmann21 updated Jul 25, 2024
6
if VPR have routing constraint like Xilinx fixed routing
#2693 opened Aug 16, 2024 by teddyisgood updated Aug 16, 2024
3D switch block updates & commenting
#2694 opened Aug 16, 2024 by vaughnbetz updated Aug 16, 2024
Issue with Multibit Adder in VTR flagship architecture
#2710 opened Sep 3, 2024 by shrekliao updated Sep 3, 2024
Multibit Adder Architecture Failure
#2717 opened Sep 9, 2024 by shrekliao updated Sep 9, 2024
VTR seems to struggle with being smart about how it packs into memories
#2718 opened Sep 12, 2024 by WhiteNinjaZ updated Sep 12, 2024
[IPA] MVP to manually test vpr --server mode
#2704 opened Aug 26, 2024 by w0lek updated Sep 12, 2024
3
Improve 3D switch block commenting and move command line option to arch file
#2722 opened Sep 13, 2024 by vaughnbetz updated Sep 13, 2024
3 tasks
Unexpected attribute 'tileable' found on node 'layout'
#2247 opened Feb 22, 2023 by zliu1Charlotte updated Sep 16, 2024
3
CLBs Positioned Far from IOs
#2727 opened Sep 17, 2024 by WindFrank updated Sep 17, 2024
[Packer] Setting Higher Target Pin Utilization When Regions are Full VPR VPR FPGA Placement & Routing Tool
#2729 opened Sep 20, 2024 by AlexandreSinger updated Sep 20, 2024
[Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer VPR VPR FPGA Placement & Routing Tool
#2731 opened Sep 20, 2024 by AlexandreSinger updated Sep 20, 2024
Overly Verbose Router Look ahead warnings
#2748 opened Sep 25, 2024 by ZohairZaidi updated Sep 25, 2024
[IntraClusterPlacement] Code Cleanups
#2732 opened Sep 20, 2024 by AlexandreSinger updated Oct 3, 2024
1 of 4 tasks
2
VPR error when trying to compile my design generated using PRGA
#2760 opened Oct 5, 2024 by polarbearsrock updated Oct 5, 2024
Packing Devices from Two Separate Parts of a Netlist into a Single CLB
#2726 opened Sep 17, 2024 by WindFrank updated Oct 10, 2024
1
Unexpected High Gain Causes Unrelated Blocks to Be Added to Clusters
#2763 opened Oct 10, 2024 by WindFrank updated Oct 13, 2024
Issue with Molecule Clustering Causing Suboptimal Placement
#2775 opened Oct 16, 2024 by WindFrank updated Oct 16, 2024
ProTip! no:milestone will show everything without a milestone.