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Parsing Errors For Nightly Test 2
#3145
opened Jun 16, 2025 by
AmirhosseinPoolad
updated Jun 16, 2025
Change RRG storage to keep (drive pt, direction) instead of (start, end)
Stale
#2491
opened Feb 20, 2024 by
duck2
updated Jun 12, 2025
Portable VTR Release with a Static Build of VTR
#3122
opened Jun 8, 2025 by
stefanpie
updated Jun 8, 2025
[TestCoverage] Failing Titanium Benchmarks for S10 Arch
#3105
opened Jun 4, 2025 by
AlexandreSinger
updated Jun 5, 2025
[GUI] Floating triangles drawn when primitive nets enabled.
#3109
opened Jun 4, 2025 by
SamuelHo10
updated Jun 4, 2025
parse_vtr_flow doesn't follow documentation
#2478
opened Jan 12, 2024 by
Stef9998
updated Jun 4, 2025
[Infra] Use Standard Strings in LibArchFPGA Physical Types
#3102
opened Jun 3, 2025 by
AlexandreSinger
updated Jun 3, 2025
[ClusterLegalizer] Code Cleanups
VPR
VPR FPGA Placement & Routing Tool
#2730
opened Sep 20, 2024 by
AlexandreSinger
updated May 16, 2025
4 of 6 tasks
[STA] Post-Implementation STA Support for Dedicated Clock Network Modeling
#3027
opened May 7, 2025 by
AlexandreSinger
updated May 14, 2025
[LibArchFPGA] Logical Models More Cleanups
#3012
opened Apr 30, 2025 by
AlexandreSinger
updated May 4, 2025
5 tasks
[Packer] Prepacker handling of pack pattern pins with net fanout > 1
#2996
opened Apr 22, 2025 by
amin1377
updated Apr 24, 2025
[AP] Using Pin Offsets During Global Placement
#2995
opened Apr 22, 2025 by
AlexandreSinger
updated Apr 22, 2025
[Pack] Unneccesary mutation of the atom to clb lookup global context in packer
#2992
opened Apr 22, 2025 by
AmirhosseinPoolad
updated Apr 22, 2025
[Pack][Timing] Pre-Cluster Timing Analysis May Not Be Aware of Molecules
#2972
opened Apr 11, 2025 by
AlexandreSinger
updated Apr 13, 2025
Use of Equivalent Sites Ambiguates PB Type Usage in Place and Route
#2888
opened Feb 7, 2025 by
petergrossmann21
updated Feb 14, 2025
[Pack] Estimating Inter-Cluster Delay Before Packing
#2890
opened Feb 8, 2025 by
AlexandreSinger
updated Feb 8, 2025
[Prepacker] Pack Molecule Data Structure Clarity
#2791
opened Oct 30, 2024 by
AlexandreSinger
updated Feb 8, 2025
4 of 9 tasks
Needed features in VTR description to represent Xilinx architecture
#2071
opened Jun 23, 2022 by
WhiteNinjaZ
updated Jan 28, 2025
7 of 12 tasks
[LibVTRUtil] Confusing API for vtr::rect
#2868
opened Jan 21, 2025 by
AlexandreSinger
updated Jan 22, 2025
Incorrect constant K-LUT primitive instantiation
#2842
opened Dec 11, 2024 by
Junius00
updated Jan 17, 2025
Do nodes of timinggraph have spatial information?
#2853
opened Dec 27, 2024 by
DuqingF
updated Jan 16, 2025
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