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Issues list

Several combinational assignments to register signals in arm_core.v
#3147 opened Jun 17, 2025 by WhiteNinjaZ
Parsing Errors For Nightly Test 2
#3145 opened Jun 16, 2025 by AmirhosseinPoolad
2
Portable VTR Release with a Static Build of VTR
#3122 opened Jun 8, 2025 by stefanpie
1
[GUI] Floating triangles drawn when primitive nets enabled.
#3109 opened Jun 4, 2025 by SamuelHo10
[TestCoverage] Failing Titanium Benchmarks for S10 Arch
#3105 opened Jun 4, 2025 by AlexandreSinger
7
[Infra] Use Standard Strings in LibArchFPGA Physical Types
#3102 opened Jun 3, 2025 by AlexandreSinger
ODIN struggles to unroll for-loop
#3057 opened May 19, 2025 by barguello
[STA] Post-Implementation STA Support for Dedicated Clock Network Modeling
#3027 opened May 7, 2025 by AlexandreSinger
9
[LibArchFPGA] Logical Models More Cleanups
#3012 opened Apr 30, 2025 by AlexandreSinger
5 tasks
1
[Packer] Prepacker handling of pack pattern pins with net fanout > 1
#2996 opened Apr 22, 2025 by amin1377
1
[AP] Using Pin Offsets During Global Placement
#2995 opened Apr 22, 2025 by AlexandreSinger
[Pack] Unneccesary mutation of the atom to clb lookup global context in packer
#2992 opened Apr 22, 2025 by AmirhosseinPoolad
[Pack][Timing] Pre-Cluster Timing Analysis May Not Be Aware of Molecules
#2972 opened Apr 11, 2025 by AlexandreSinger
1
genfasm command failing in VPR flow
#2963 opened Apr 5, 2025 by muthu-iisc
Parmys Failed to load architecture file
#2927 opened Mar 11, 2025 by huma4921
[Pack] Estimating Inter-Cluster Delay Before Packing
#2890 opened Feb 8, 2025 by AlexandreSinger
Use of Equivalent Sites Ambiguates PB Type Usage in Place and Route
#2888 opened Feb 7, 2025 by petergrossmann21
9
Unable to generate odin_ii
#2879 opened Feb 3, 2025 by aryan-1307
5
[LibVTRUtil] Confusing API for vtr::rect
#2868 opened Jan 21, 2025 by AlexandreSinger
3
Do nodes of timinggraph have spatial information？
#2853 opened Dec 27, 2024 by DuqingF
1
Incorrect constant K-LUT primitive instantiation
#2842 opened Dec 11, 2024 by Junius00
3
Questions about FPGA Routing Architecture Visualization
#2837 opened Dec 4, 2024 by LucaMartis00
16
Wire lookahead runtime scales poorly with number of switch/segment types
#2811 opened Nov 15, 2024 by petergrossmann21
5
SDC Parsing causes assertion error for specific netlist sweeping option combination
#2809 opened Nov 15, 2024 by petergrossmann21
Troubleshooting RR graphs with poor router performance
#2803 opened Nov 7, 2024 by petergrossmann21
4
ProTip! Exclude everything labeled bug with -label:bug.